Semiconductor integrated circuit device

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C326S086000, C326S021000, C326S108000

Reexamination Certificate

active

07038486

ABSTRACT:
A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

REFERENCES:
patent: 6384621 (2002-05-01), Gibbs et al.
patent: 6535047 (2003-03-01), Mughal et al.
patent: 6545522 (2003-04-01), Mughal et al.
patent: 6570406 (2003-05-01), Tang et al.
patent: 6621352 (2003-09-01), Matsumoto et al.
patent: 6628223 (2003-09-01), Nagano
patent: 6836143 (2004-12-01), Song
patent: 6909312 (2005-06-01), Mitsumoto
patent: 10-242835 (1997-02-01), None

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