Semiconductor integrated circuit device

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement

Reexamination Certificate

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Details

C326S030000, C326S031000, C326S032000, C326S033000, C326S034000

Reexamination Certificate

active

07123045

ABSTRACT:
When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released.

REFERENCES:
patent: 4818901 (1989-04-01), Young et al.
patent: 4918336 (1990-04-01), Graham et al.
patent: 5426376 (1995-06-01), Wong et al.
patent: 5610537 (1997-03-01), Hastings
patent: 6236248 (2001-05-01), Koga
patent: 11-046120 (1999-02-01), None
patent: 2001-053558 (2001-02-01), None

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