Semiconductor integrated circuit device

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Reexamination Certificate

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C365S185090, C365S189040

Reexamination Certificate

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06982900

ABSTRACT:
A semiconductor integrated circuit device includes a data bit storage memory which stores data bits, a code bit storage memory which stores code bits, and an ECC circuit. The code bit storage memory is controlled independently from the data bit storage memory. The ECC circuit corrects an error of at least one bit contained in one of the data bits and code bits by use of the data bit and code bit. The operation of writing the code bit corresponding to the data bit into the code bit storage memory when a data write command is received is performed at least one cycle after the data bit is written into the data bit storage memory.

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patent: 6614685 (2003-09-01), Wong
patent: 2003/0093744 (2003-05-01), Leung et al.
patent: 2005/0036371 (2005-02-01), Kushida
Kazutami Arimoto, et al., “A Speed-Enhanced DRAM Array Architecture With Embedded ECC”, IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 11-17.
U.S. Appl. No. 10/853,193, filed May 26, 2004, Hirabayashi.
U.S. Appl. No. 10/930,767, filed Sep. 1, 2004, Hirabayashi.

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