Semiconductor integrated circuit device

Static information storage and retrieval – Systems using particular element – Flip-flop

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365156, 257904, G11C 1140

Patent

active

056108567

ABSTRACT:
An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.

REFERENCES:
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4853894 (1989-08-01), Yamanaka et al.
patent: 5122857 (1992-06-01), Ikeda et al.
patent: 5281843 (1994-01-01), Ochii
patent: 5377139 (1994-12-01), Lage

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