Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-28
2005-06-28
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C257S207000, C257S338000, C257S369000
Reexamination Certificate
active
06912697
ABSTRACT:
In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.
REFERENCES:
patent: 5105252 (1992-04-01), Kim
patent: 5311048 (1994-05-01), Takahashi
patent: 5376839 (1994-12-01), Horiguchi
patent: 5434436 (1995-07-01), Tamiguchi
patent: 5619420 (1997-04-01), Breid
patent: 5663662 (1997-09-01), Kurosawa
patent: 5763907 (1998-06-01), Dallavalle et al.
patent: 5801407 (1998-09-01), Yamada
patent: 5898595 (1999-04-01), Bair et al.
patent: 2269049 (1994-01-01), None
patent: 60-130138 (1985-07-01), None
patent: 63-090847 (1988-04-01), None
patent: 60-085200 (1994-03-01), None
patent: 6-120439 (1994-04-01), None
patent: 6-334010 (1994-12-01), None
patent: 7-235608 (1995-09-01), None
patent: 60-017183 (1996-01-01), None
patent: WO 97/21247 (1997-06-01), None
Kuroda et al., “A 0.9V 150MHz 10mW 4mm22-D Discrete Cosine Transform Core Processor With Variable Threshold Voltage Scheme”, ISSCC96.
Kuroda et al., “A High-Speed Low-Power 0.3μm CMOS Gate Array With Variable Threshold Voltage (VT) Scheme”, IEEE 1996 Custom Integrated Circuits Conference.
Murry, W., “Chapter 5: CMOS Technology”, Zusetsu Cho Eruesuai Koqaku (illustrated ULSI Engineering in English), pp. 167-191 (in Japanese with English translation).
Shibata Ryuji
Shimada Shigeru
Antonelli Terry Stout & Kraus LLP
Garbowski Leigh M.
Renesas Technology Corp.
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