Semiconductor integrated circuit device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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C365S185050, C365S189120, C365S200000

Reexamination Certificate

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06894944

ABSTRACT:
To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.

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Takai et al., “A 250Mv/s/pin 1Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Scheme”, 1999 IEEE Int'l Solid-State Circuits Conference, pp. 418-419.

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