Semiconductor integrated circuit device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S233100, C365S189011

Reexamination Certificate

active

06870756

ABSTRACT:
A semiconductor integrated circuit device provided with a SRAM realizing low power consumption and high speed is to be provided. Out of memory circuits which cause a timing generator circuit which selects writable and readable memory cells with the address selector circuit, conveys write signals to a memory cell selected by a write circuit, conveys read signals from a memory cell selected by a read circuit, and receives a clock signal, to generate operational timing signals to be conveyed to an address selector circuit, a write circuit and a read circuit, a circuit in which the operational timing is not too tight is configured of a higher threshold voltage MOSFET than the MOSFETs of other circuits.

REFERENCES:
patent: 5668770 (1997-09-01), Itoh et al.
patent: 6597629 (2003-07-01), Raszka et al.
patent: 4-344395 (1991-05-01), None
patent: 9-51042 (1996-02-01), None
patent: 2002-100190 (2000-09-01), None

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