Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2005-07-19
2005-07-19
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S230060, C365S226000
Reexamination Certificate
active
06920071
ABSTRACT:
A semiconductor integrated circuit device endowed with memory circuits achieving high operation margin and low energy consumption with high speed and high integration. Composing a memory cell with a MOSFET having a first threshold voltage corresponding to a first voltage and supplying a selection signal corresponding to said first voltage to a word line by a word driver driven at said first voltage. Corresponding to a second voltage smaller than said first voltage, forming a selection signal sending to said word driver by a decoder comprising MOSFET with a second threshold voltage smaller than said first voltage, operating at said first voltage, and installing a first level shifting circuit including inverter circuits that form a selection signal corresponding to said first voltage by receiving a selection signal corresponding to said second voltage. Thereby, high operation margin and low energy consumption with high speed and high integration can be achieved.
REFERENCES:
patent: 6269047 (2001-07-01), Kohno
patent: 6385118 (2002-05-01), Fujisawa et al.
patent: 5-120882 (1993-05-01), None
H. Kawaguchi et al., “A 0.5V, 400MHz, V00-Hopping Processor with Zero-VthFD-SOI Technology”, 2003 IEEE International Solid-State Circuits Conference, Session 6, Low-Power Digital Techniques, Paper 6.3, Feb. 10, 2003.
Higeta Keiichi
Kawata Takahiro
Nakahara Shigeru
Hitachi , Ltd.
Miles & Stockbridge P.C.
Phan Trong
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