Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-05-05
2004-07-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189050
Reexamination Certificate
active
06765831
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-302754, filed Oct. 17, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a destructive read-out semiconductor memory in which cell data is destructed upon read.
2. Description of the Related Art
Semiconductor memory data read methods are roughly classified into destructive read-out and non-destructive read-out.
In destructive read-out, memory information is lost in data read and must be restored. Examples of destructive read-out semiconductor memories are a DRAM (Dynamic Random Access Memory) and FeRAM (Ferroelectric Random Access Memory). Known examples of an FeRAM are disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2000-349248 and U.S. Pat. No. 6,038,162.
In non-destructive read-out, memory information is not lost in data read and need not be restored. Examples of non-destructive read-out semiconductor memories are, an SRAM (Static Random Access Memory) and EEPROM (Electrically Erasable Programmable Read Only Memory).
Semiconductor memory interfaces are classified into two types: a synchronous interface and asynchronous interface.
The synchronous interface starts operation in response to, e.g., input of a sync signal such as a RAS (Row Address Strobe) signal or CAS (Column Address Strobe) signal. The asynchronous interface shifts to the next operation in response to transition of an external address signal.
A general non-destructive read-out semiconductor memory can shift to the next operation within a time shorter than the cycle time even if the address changes during read operation. This implements an asynchronous interface which shifts to the next operation in response to transition of an external address signal.
To the contrary, once read operation starts, a destructive read-out semiconductor memory cannot shift to the next operation until data is restored in a cell. For this reason, the destructive read-out semiconductor memory generally adopts a synchronous interface which operates in response to, e.g., input of a sync signal.
To implement an asynchronous interface in the destructive read-out semiconductor memory, memory array operation starts a predetermined time (to be referred to as a skew time hereinafter) after transition of an external address is detected. Within a chip, the operation waits for the skew time after transition of an external address signal is detected. If no address changes during this period, memory operation starts. An example of the operation sequence is shown in FIG.
13
.
As shown in
FIG. 13
, an external address signal changes at time T1. An address buffer waits for a skew time Tw after the address transition (Wait: arrow (
1
)). The address buffer waits by changing a latch circuit (latch) in the address buffer to a through state (through), a buffer circuit (buffer) in the address buffer to a close state (close), and an internal address signal (Internal Address) to an invalid state (Invalid).
At time T2 before the lapse of the skew time Tw, the external address signal changes again. The address buffer waits for another skew time Tw after this address transition (arrow (
2
)).
If no address changes by time T3 upon the lapse of the skew time Tw, the address buffer shifts to the next operation. At time T3, the latch circuit changes from the through state to the latch state (latch), and an output from the latch circuit is fixed. The buffer circuit is changed from the close state to an open state (open), and the internal address signal is changed from the invalid state to a valid state (Valid). Accordingly, decode processing (Address decode) of the internal address signal starts (arrow (
3
)).
Upon the lapse of a decode time Td from time T3, decode processing ends, and a corresponding word line (Word Line) changes from the invalid state (Invalid) to the valid state (Valid). At corresponding time T4, a memory array control signal (Array Control) for controlling the memory array changes from the invalid state (Invalid) to the valid state (Valid), and memory array control starts. Read/restore operation (Read/Restore: arrow (
4
)) is performed, and precharge operation (Precharge: arrow (
5
)) and data output (Output) are executed from time T5. At time T6, one cycle ends.
The asynchronous memory interface which performs this operation waits for the skew time Tw until memory operation actually starts after transition of an external address signal. The access time is prolonged by the skew time Tw, compared to the synchronous memory interface which starts operation in synchronism with a chip enable signal or the like.
In the operation sequence shown in
FIG. 13
, let Tw be the skew time; Td, the decode time necessary for decode processing of an address signal; Tr, the read/restore time until data is output after memory array control starts; and Tp, the time (or precharge time) until the end of one cycle after data is output.
In this case, the access time of a semiconductor memory having a synchronous memory interface is given by
Td+Tr
The cycle time is given by
Td+Tr+Tp
To the contrary, the access time of a semiconductor memory having an asynchronous memory interface is prolonged to
Tw+Td+Tr
The cycle time is prolonged to
Tw+Td+Tr+Tp
BRIEF SUMMARY OF THE INVENTION
A semiconductor integrated circuit device according to an aspect of the present invention comprises: a memory array which includes a memory cell array in which destructive read-out memory cells are integrated; an address buffer which outputs an internal address signal corresponding to an input external address signal; an address decoder which decodes the internal address signal and outputs a memory cell selection signal for selecting the memory cell in the memory cell array on the basis of a decode result; and a controller which parallel-executes wait processing of keeping the address buffer in a wait state until lapse of a skew time after transition of the external address signal is detected, and decode processing until the memory cell selection signal changes from an invalid state to a valid state in response to output of the internal address signal.
REFERENCES:
patent: 5887272 (1999-03-01), Sartore et al.
patent: 6038162 (2000-03-01), Takata et al.
patent: 6301145 (2001-10-01), Nishihara
patent: 6473352 (2002-10-01), Nishino et al.
patent: 2000-349248 (2000-12-01), None
Mun-Kyu Choi, et al. “A 0.25&mgr;m 3.0V 1T1C 32Mb Nonvolatile Ferroelectric Ram With Address Transition Detector(ATD) and Current Forcing Latch Sense Amplifier(CFLSA) Scheme,” 2002 IEEE International Solid-State Circuits Conference, Vol. 1, 2002, pp. 162-163.
Oikawa Kohei
Shiratake Shinichiro
Takashima Daisaburo
Elms Richard
Nguyen Tuan
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