Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-11-13

2003-02-04

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S189011, C365S230060, C365S207000

Reexamination Certificate

active

06515892

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and relates in particular to a high reliability, large capacity semiconductor memory circuit.
BACKGROUND OF THE INVENTION
Semiconductor memories are broadly classified into RAM (random access memories) and ROM (read only memory) devices. Among these devices, the dynamic RAM (DRAM) is used in the largest numbers as the main memory for computers. The memory cells that store the information are composed of one capacitor and a transistor to read out the charge stored on that capacitor. This memory cell can form the smallest structural element on the RAM and is therefore ideal for use on a large scale. Accordingly, this large scale use results in making these memory cell devices ideal for mass production at a low price.
However, the DRAM has a problem in that operation tends to be unstable. The largest cause of this instability is that the memory cell itself has no amplifying effect and therefore the read out signal voltage from the memory cell is small and the memory cell operation is susceptible to all kinds of random noise. Another drawback is that the information charge stored in the capacitor is lost due to the leakage current in the pn junction within the memory cell. Before this charge is lost, a refresh (rewrite) operation is performed periodically on the memory cell to retain the memory information stored in the memory cell. The period is referred to as the refresh period and currently requires approximately 100 milliseconds, however this refresh period becomes longer as the memory capacity increases. In other words, the leakage current must be limited but restricting the leakage current becomes more and more difficult as the elements become smaller.
A memory to solve these problems was the ROM and the flash memory in particular. As is well known, the flash memory is at least as small as a DRAM cell and the memory cell has internal gain so that the signal voltage is essentially large, and operation is therefore stable. A storage charge is also accumulated in the storage node enclosed by an insulator film so that like the DRAM, there is no current leakage from the pn junction and a refresh operation is not required. However, a weak tunnel current flows to accumulate the charge in the storage mode so that the write time is extremely long. Also, repeating the write operation causes electrical current to flow in the insulator film and the insulator film gradually deteriorate and finally the insulator film becomes a conductive film that is unable to retain information.
The ROM device is therefore generally limited to about 100,000 write operations. In other words, the flash memory cannot be utilized as a RAM. The DRAM and flash memory therefore both have a large capacity memory and respective advantages and disadvantages. The particular advantages of each device have to be considered when using the device.
A method of the known art for a three transistor cell comprised of a storage MOSFET to store an information voltage in a gate, and a write MOSFET to write an information voltage in a gate was disclosed for instance in “Ultra LSI Memories” Baifukan, Nov. 5, 1994 Kiyoo Itoh, PP. 12-15. The three-transistor cell of this type had an amplification function in the cell itself so that the signal voltage appearing in the data line was large, and read out was totally non-destructive however this device also had problems since the peripheral circuits for read and write operations were complicated and difficult to use so that the three transistor cell was not practical to use.
In view of the above problems with the prior art, it is an object of the present invention to provide a semiconductor integrated circuit device having a memory circuit with simple circuit structure that is also easy to use.
Yet another object of the present invention is to provide a semiconductor integrated circuit device having a memory circuit that is both high speed and nonvolatile. The above mentioned and other new features and objects of this invention will be apparent to one skilled in the art from the description of this invention and the accompanying reference drawings.
SUMMARY OF THE INVENTION
A simple description of the concept of the invention as disclosed in this application is as follows. A semiconductor device has a memory cell array comprised of memory cells containing a write transistor and a storage MOSFET for holding an information voltage in the gate, a word line intersecting with a write data line for conveying write information voltages and an intersecting read line for conveying read information signals corresponding to the on or off state of the storage MOSFET memory cell, the control terminals of the write transistors of the memory cell are connected by the word lines and the read signal is output on the corresponding read data line in response to the select signal from the write transistor control terminals, and one read data line is selected from among a plurality of read data lines by the data line select circuit and is connected to either a first or second common data line, the selected read data line is precharged to a first voltage potential in the non-select period, in a first select period that word line is selected for read out and discharged to a second voltage potential by the on status of the storage MOSFET of the memory cell, the first and second common data lines are precharged to a third voltage potential between the first and second voltage potentials in the non-select period, the read signal appearing in the first select period on the read data line selected by the data line select circuit and in one common data line corresponding to the dispersed charge are amplified using the precharge voltage of another common data line as the reference voltage, after the write signal is conveyed on the write data line, when necessary, in the second select period the word lines are set to a high voltage and the write transistor is set to on status to perform write or rewrite in the memory cell.
A simple description of another representative concept of the invention as disclosed in this application is as follows. Namely, a semiconductor device has a memory cell array comprised of memory cells containing a write transistor and a storage MOSFET for holding an information voltage in the gate, a word line intersecting with a write data line conveying write information signals and an intersecting read data line conveying read information signals corresponding to the on or off state of the storage MOSFET of the memory cell, the control terminals of the write transistors of the memory cell are connected by the word lines, and the read signal is output on the corresponding read data line in response to the select signal from the control terminals, a sense amplifier comprised of a CMOS latch structure is formed between the write data line and the read data line, that read data line is precharged to a first voltage potential in a first period, that write data line is precharged to a second voltage smaller than the first voltage in the first period, the word line is selected in a second period and the read data line is discharged to a third voltage potential by the on status of the storage MOSFET of the memory cell, the sense amplifier is set to operating status after the read data line has been set to the first voltage or the third voltage corresponding to the memory cell information voltage and the high level or low level state is amplified according to the operating voltage of the sense amplifier, and a data line select circuit selects one pair of data lines from among a plurality of pairs comprised of read data lines and their corresponding write data lines and connect that data line pairs to a first and second common data line.


REFERENCES:
patent: 4771323 (1988-09-01), Sasaki
patent: 4920391 (1990-04-01), Uchida
patent: 5675160 (1997-10-01), Oikawa
patent: 6314017 (2001-11-01), Emori et al.
patent: 6388934 (2002-05-01), Tobita
patent: 6452858 (2002-09-01), Hanzawa et al.

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