Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-06-04

2003-04-22

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S200000, C365S225700

Reexamination Certificate

active

06552960

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2001-168705, filed on Jun. 4, 2001, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor integrated circuit architectures and more particularly to semiconductor integrated circuitry with a plurality of functional circuits controllable by multiple control signals respectively.
2. Description of the Related Art
Various types of currently available semiconductor memory devices such as dynamic random access memory (DRAM) chips are customarily designed to employ redundancy circuit schemes for defect cell repair or “rescue” purposes. In redundancy circuit-embedded memory chips, there are prepared a redundant row cell array and a redundant column cell array in addition to a normal cell array. And, upon inputting of the address of a defective or “fault” cell, control is performed to replace a defective row with a redundant row or replace a defective column by a redundant column. To achieve such replacement controllability, memory chips come with built-in defect address storage circuitry including but not limited to more than one fuse circuit. The defect address storage circuitry offers an ability to write or “programs” one or more defect addresses based on test results of the memory chip of interest.
A typical configuration of certain part of such prior known semiconductor memories is shown in
FIG. 16
, which part has fuse information latching functionality. The circuit shown herein includes a plurality of fuse latch circuits
11
, each of which is operable to automatically read fuse data as has been programmed after power-up and then latch it therein. Thereafter, the latch data will be used to perform An address replacement control operation(s). In order to detect a powerup event and automatically initialize the fuse latch circuits
11
, there are provided a power-on circuit
10
and a fuse latch initialize circuit (initializer)
13
operatively responsive to receipt of an output of it for performing initialization of fuse latch circuits
11
.
The fuse latch initialize circuit
13
receives a power-on signal PWRON as input thereto from the power-on circuit
10
and then generates based on this signal both a precharge signal BFPRCH which is used to uniformly precharge the fuse latch circuits
11
and a fuse set signal FSET for setting up fuse information at the fuse latch(es). The precharge signal bFPRCH and fuse set signal FSET are input to each fuse latch circuit
11
, which then outputs fuse information initialized by these signals toward an output end FBLWN.
A configuration of one fuse latch circuit
11
is shown in
FIG. 17
whereas an arrangement of the fuse latch initialize circuit
13
is illustrated in
FIG. 18. A
configuration of the power-on circuit
10
is depicted in FIG.
19
. As shown in
FIG. 19
, the power-on circuit
10
operates so that when a power supply voltage Vcc reaches a prespecified potential level after power-up, an inverter INV
31
inverts, to which an intermediate or “midway” voltage as generated by potential division of resistors R
1
and R
2
is input. In responding to receipt of an output of this inverter INV
31
, respective ones of serially connected inverters INV
32
, INV
33
and INV
34
will further be inverted sequentially, causing an output signal PWRON to finally change in potential from “Low” or “L” level to “High” (“H”) level.
As shown in
FIG. 18
, in the fuse latch initialize circuit
13
, a level transition detection circuit
61
that consists of inverters INV
11
to INV
13
and a NAND gate G
1
detects a level transition of the power-on signal PWRON from “L” to “H” level, resulting output of a precharge signal bFPRCH which is a negative logic pulse(s). In addition, a delay circuit
62
and a level transition detector circuit
63
for detection of an “L”-to-“H” level transition of an output thereof permit output of a fuse set signal FSET with a time lag or delay from the issuance of the precharge signal bFPRCH. The level transition detector circuit
63
has inverters INV
21
-
23
and a NAND gate G
2
in a similar manner to that of the level transition detector circuit
61
, with a further inverter INV
24
provided at its output, resulting in the fuse set signal FSET becoming a positive logic pulse(s). The precharge signal bFPRCH and fuse set signal FSET are adjustable in timing by the delay circuit
62
.
As shown in
FIG. 17
the fuse latch circuit
11
is configured from a fuse element F that is programmable by laser irradiation and a latch
111
. The laser-programmable fuse F is such that programming is done based on wafer test results in such a way as to cut off a portion corresponding to a defect address. Upon power-up, a P-channel metal oxide semiconductor (PMOS) transistor QP turns on in response to receipt of a precharge signal bFPRCH, causing “H” level of supply voltage Vcc to be precharged at a node A. Thereafter, upon supplement of a fuse set signal FSET, the node A is discharged through an N-channel MOS (NMOS) transistor QN and the fuse F in case fuse F is not yet cut off; if fuse F is cut then it retains “H” level. To be brief, the fuse information indicative of whether the fuse is already cut or not yet cut—namely, electrically open-circuit or short-circuit—is read and held at the latch
111
while letting a finally obtainable output signal FBLWN be set at “L” if fuse F remains conductive or alternatively set at “H” if fuse F is cut and made nonconductive.
To enable the fuse latch circuit
11
to perform this operation, the precharge signal bFPRCH as output from the fuse latch initialize circuit
13
is specifically designed so that its negative pulse width has a length of time period long enough to permit the node A to be fully precharged whereas the fuse set signal FSET is such that its positive pulse width is set at a time long sufficient to allow node A to discharge.
Turning to
FIG. 20
, there is shown an operation timing chart covering from supply voltage rise-up to setup of the fuse information. A delay time X shown herein of from a timing at which the precharge signal bFPRCH transitions to “L” level up to a timing whereat the fuse set signal FSET potentially shifts to “H” level is the delay time that is set by the delay circuit
62
within the above-discussed fuse latch initialize circuit
13
. In order to enable the fuse latch circuit
11
to properly read its contained fuse information and then latch it therein, it is inevitable to avoid any situation in which both the PMOS transistor QP and the NMOS transistor QN turn on at a time. Accordingly, the delay time T must be set at specific values greater than the pulse width of precharge signal bFPRCH.
Assume here that the delay time &tgr; is less than the pulse width of the precharge signal bFPRCH for explanation purposes only. In this case, in a fuse latch circuit
11
with its fuse being not cut yet, the node A begins discharging due to the NMOS transistor QN at a time point during precharging due to the PMOS transistor QP, resulting in collision or impingement of such discharge and charge-up events. Consequently, it will no longer be able to accurately determine whether the node A potentially drops down at on-chip ground or “source” level Vss while the fuse set signal FSET is kept at “H” level, i.e. within a turn-on time period of NMOS transistor QN, which would lead to the lack of any reliable establishment of the latch state in a way as expected. For the very reason, it should be strictly required that the delay time &tgr; be set in value at the negative pulse width of precharge signal bFPRCH with a sufficiently significant margin added thereto.
However, even if a long enough delay time &tgr; is secured in the fuse latch initialize circuit
13
for use as the source for generation of the precharge signal bFPRCH and fuse set signal FSET, there is no guarantee that such delay time &tgr; still remains in cases

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