Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-07-05

2003-03-25

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S207000, C365S051000

Reexamination Certificate

active

06538946

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and, in particular, to a technique effectively applicable to a sense amplifier of a DRAM (Dynamic Random Access Memory).
The DRAM (Dynamic Random Access Memory) has a memory cell formation region in which a plurality of memory cells are formed, and a peripheral circuit region in which circuits required for writing and reading information to and from these memory cells, for example, a sense amplifier or the like are formed. Each memory cell comprises a capacitor C, and a transfer MISFETQs whose one end is connected to the capacitor C in series.
These memory cells are formed at a rate of one to two of intersecting points, as shown in
FIG. 17
, at each of which a word line WL comprising a gate electrode of the transfer MISFETQs and a bit line BL connected to the other end of the transfer MISFETQs intersect.
Meanwhile, a sense amplifier SA is a circuit for amplifying a potential difference between bit lines, and is formed in a sense amplifier formation region, and further, is connected between bit lines (e.g., between bit lines BL
3
B and BL
3
T), as shown in FIG.
18
. Moreover, in the sense amplifier formation region, there are formed a pre-charge circuit PC connected between bit lines, and a Y-switch circuit YS connected between a bit line and an input/output line, and the like in addition to the sense amplifier.
SUMMARY OF THE INVENTION
However, as the interval between the bit lines become narrower in accordance with fineness of the memory cells in size, the sense amplifier SA, pre-charge circuit PC, Y-switch circuit, and the like must be made fine as corresponding thereto.
But, in order to write and read information at a high speed, gate dimension and diffusion layer constant must be secured to some degree. Further, a MISFET constituting the sense amplifier or the like can not be made fine similarly to the transfer MISFETQs constituting the memory cell.
Therefore, even if the memory cell is made fine, a chip occupancy area of DRAM is difficult to reduce because it is difficult to make a peripheral circuit such as a sense amplifier or the like fine.
In particular, in case where memory cells are formed at all the intersecting points of word lines and bit lines (see FIG.
1
), it is possible to reduce the memory cell area to half (
4
F
2
) of the case (
8
F
2
) shown in FIG.
17
. However, since the interval between bit lines becomes narrower, there occurs a problem in an occupancy area of the peripheral circuit such as a sense amplifier.
Moreover, in the sense amplifier formation region, a region of arranging wirings for supplying a pre-charge potential to the pre-charge circuit, wirings for coming into contact with the input/output line, and the like must be secured between the narrow bit lines. However, in particular, in case of forming the memory cell at all the intersecting points of the word lines and the bit lines, the bit lines extend to the sense amplifier formation region without interposing shared MISFETs (SM) shown in
FIGS. 17 and 18
, so that limits to arrangement of the wirings occur as described hereinafter.
An object of the present invention is to provide reduction of the occupation area in the sense amplifier formation region. Also, other object of the present invention is to provide layouts of the sense amplifier formation region, which can correspond to bit lines of the fined memory cells.
The above-mentioned and other objects and novel features will be apparent from description of the following specification and the accompanying drawings.
The following is a brief description on typical inventions disclosed in the present application.
In the semiconductor integrated circuit device of the present invention, the first and second column selecting circuit regions and the first and second pre-charge circuit regions are respectively formed on both ends of the sense amplifier formation region. And, if the first bit line (BL
2
T) extending from the first memory cell formation region of the first and second memory cell formation regions arranged on both sides of the sense amplifier formation region, is simply made to extend to and arrive at the sense amplifier circuit region via the first pre-charge circuit region and the first column selecting circuit region, then a wiring region for arranging wirings other than bit lines can be secured on the extended first bit line.
Moreover, the sense amplifier circuit region comprises a first region for forming an n-channel type MISFET constituting a first sense amplifier, a second region for forming an n-channel type MISFET constituting a second sense amplifier, a third region for forming a p-channel type MISFET constituting the second sense amplifier, and a fourth region for forming a p-channel type MISFET constituting the second sense amplifier. And, the second and fourth regions are arranged in a state of being shifted in a direction perpendicular to the bit line relative to the first and third regions. Therefore, an interval between the bit lines connected to the sense amplifier can be made narrower.


REFERENCES:
patent: 5265050 (1993-11-01), McLaury
patent: 5291432 (1994-03-01), Furutani
patent: 6046924 (2000-04-01), Isobe et al.
patent: 6046950 (2000-04-01), Kim
patent: 6165592 (2000-12-01), Kanai et al.
patent: 6256246 (2001-07-01), Ooishi
patent: 6295241 (2001-09-01), Watanabe et al.
patent: 2001/0013659 (2001-08-01), Noda et al.

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