Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-03-01

2002-08-06

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S203000, C257S390000, C257S306000

Reexamination Certificate

active

06429476

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and to the method of its fabrication; and, more particularly, the invention relates to a semiconductor integrated circuit having a DRAM (dynamic random access memory) with miniaturized memory cells
A DRAM memory cell, which is formed at the intersection of word lines and bit lines that are provided in a matrix pattern over the major surface of a semiconductor substrate, comprises a single memory-cell-selecting MISFET (metal-insulator-semiconductor field-effect transistor) and a single data-storage capacitor connected in series thereto. The memory-cell-selecting MISFET mainly comprises a gate oxide film, a gate electrode that is configured in a single unit with a word line, and a pair of semiconductor regions that form the source and drain regions. The bit line, which is provided over the memory-cell-selecting MISFET, is electrically connected to either the source region or the drain region. The data-storage capacitor, which is also provided over the memory-cell-selecting MISFET, is electrically connected to the other region, source or drain.
To compensate for the reduction in the capacitance of the data-storage capacitor, which accompanies the miniaturization of the memory cells, a stacked capacitor configuration, in which the data-storage capacitor is provided over the memory-cell-selecting MISFET, has been used in the DRAMs of recent years. The stacked capacitor configuration can roughly be classified into the following two configurations: a capacitor under-bit-line (CUB) configuration in which the data-storage capacitor is provided below the bit line, and a capacitor-over-bit-line (COB) configuration in which the data-storage capacitor is provided over the bit line.
In order to increase the capacitance of the data-storage capacitor, the surface area of the data-storage capacitor must be increased by an upward elongation of the capacitor's semiconductor form. In this case, however, if the CUB configuration, in which the data-storage capacitor is provided below the bit line, is to be employed, the aspect ratio of the contact hole that connects the bit line and the memory-cell-selecting MISFET significantly increases, and, as a result, the complete formation of the hole will become difficult. Accordingly, when the above two stacked capacitor configurations are compared, the COB configuration, in which the data-storage capacitor is provided over the bit line, is more suitable for the miniaturization of memory cells than the CUB configuration.
In the large-scale DRAMs that have appeared recently, for example, 64-Mbit DRAMs and
256-
Mbit DRAMs, it has become difficult to obtain enough storage capacitance by applying a simple upward elongation of the data-storage capacitor's configuration to increase its surface area. Accordingly, the use of a material with a high-dielectric constant for a capacitance-insulating film has been investigated. Such materials include Ta
2
O
5
(tantalum pentoxide), (Ba, Sr) TiO
3
(barium strontium titanate; hereinafter abbreviated as BST), or SrTiO
3
, (strontium titanate; hereinafter abbreviated as STO).
In official Patent Gazettes H. 11-186518, that corresponds to U.S. application Ser. No. 9/209,013 (filed on Dec. 11, 1998), and H. 11-238862, that corresponds to U.S. application Ser. No. 9/215,270 (filed on Dec. 18, 1998), a DRAM having COB memory cells is disclosed. The process of fabricating the DRAM disclosed in these Official Patent Gazettes has been simplified, in that the bit line and the first-layer wiring of the peripheral circuits are formed in the same single step. The bit line and the first-layer wiring are made of, for example, a two-layered conductive film in which a W (tungsten) film is deposited over a TiN (titanium nitride) film.
In the DRAM disclosed in official Patent Gazette H. 11-186518, when the bit line and the first-layer wiring are formed by patterning the two-layered conductive film, the TiN film that configures part of the bit line and part of the first-layer wiring of the peripheral circuits is utilized as an etching stopper that can prevent etching of the W plug inside the contact hole that connects the first-layer wiring with the MISFET of the peripheral circuits. In the DRAM disclosed in the Official Patent Gazette H. 11-238862, the first-layer wiring of the peripheral circuits is connected to the source and drain of the MISFET without the interposition of a plug. In this configuration, the TiN film under the W film is utilized as a barrier material to prevent the forming of an undesirable silicide layer as a result of reaction at the interface between the W film and the silicon substrate.
In the Official Gazette H. 11-214650, a DRAM is disclosed wherein the bit line and the first-layer wiring of the peripheral circuits are formed concurrently by a so-called Damascene method. In the Damascene method, a two-layered conductive film, comprising a WN (tungsten nitride) film and a W film that is deposited over that, is embedded inside the wiring groove that is formed in the insulating film. In this case, the WN film under the W film acts not only as an adhesive film between the W film and the insulating film in the Damascene configuration, but also as a barrier material which prevents the growth of an undesirable silicide layer at the interface between the W film and the silicon substrate.
SUMMARY OF THE INVENTION
The DRAM configuration to which the method of the present invention is applied is characterized by:
a COB configuration in which the data-storage capacitor is formed over the bit line so that the capacitance of the data-storage capacitor can be secured;
a high-dielectric film, for example Ta
2
O
5
, (tantalum pentoxide), as a capacitance-insulating film;
a refractory-metal bit line, for example W, the low resistivity of which improves the signal delay quality; and
a concurrent forming of the bit line and the first-layer wiring of the peripheral circuit, which reduces the number of fabrication process steps.
In a DRAM of this configuration, since a through hole that electrically connects the data-storage capacitor with the memory-cell-selecting MISFET is formed between adjacent bit lines, the width of the bit line needs to be reduced to 0.1 &mgr;m or less to ensure a margin against the possibility of a short-circuit forming between the bit line and the plug that has been embedded inside the through hole.
When forming a 0.1-&mgr;m-or-narrower bit line by patterning the W film that has been deposited over the insulating film, for example, silicon oxide, the inventors have found that a segregation occurs at the grain boundaries of the W that forms the bit line when high-temperature processing is applied to crystallize the high-dielectric constant material, for example Ta
2
O
5
, which forms the capacitance-insulating film of the data-storage capacitor.
The object of this invention is to provide a technique that can effectively prevent wiring breaks in the bit lines of a DRAM that has miniaturized memory cells.
The object and novel features of this invention will be clarified by the following description together with the accompanying drawings. A typical example of the invention disclosed in this application is briefly summarized in the following.
The semiconductor integrated circuit device of this invention comprises: memory cells including, a memory-cell-selecting MISFET, which is formed over the major surface of a semiconductor substrate, with a gate electrode that is configured a single unit with a word line; and a data-storage capacitor that is formed over a second insulating film which covers the bit line and that is electrically connected to the other part, either source or drain, of the memory-cell-selecting MISFET; and a bit line that is formed over a first insulating film which covers the memory-cell-selecting MISFET and that is electrically connected to either the source or drain of the memory-cell-selecting MISFET; wherein compressive stress is applied to the conductive film that configures the bit lin

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