Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-02-02
2002-01-15
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S115000, C326S121000
Reexamination Certificate
active
06339344
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device. More specifically, the invention relates to technology that can be effectively utilized for an input circuit in a general-purpose semiconductor integrated circuit device such as a dynamic RAM (random access memory).
Through the search after the present invention has been finished, the present inventors have been informed of the presence of the inventions disclosed in Nippon Electric Corporation, “NEC Technical Journal”, Vol. 50, No. 3, 1997, pp. 23-27 (Development of a 64-Megabit DRAM of the Third Generation), Japanese Patent Laid-open No. 104726/1994 and Japanese Patent Laid-open No. 143184/1995, that appear to be related to the input circuit of the present invention that will be described later. The above literatures suggest the use of a differential amplifier in the input circuit, but are quite silent concerning the method of operating the input circuit of the present invention that will be described later.
SUMMARY OF THE INVENTION
The voltage levels of input signals input to semiconductor integrated circuit devices such as dynamic RAMs are standardized depending on the interfaces such as SSTL, LVTTL, LVCMOS, etc. For the LVTTL and LVCMOS interfaces in which the signal level has a full amplitude corresponding to the operation voltage, there is used an input buffer comprising a CMOS inverter circuit. For the SSTL employing a small amplitude with the center voltage of the operation voltage as a center, on the other hand, there is used a differential amplifier circuit.
Two kinds of the input buffers are formed so as to be applied to any one of the above-mentioned interfaces, and any one is finally determined by the metal option, so that most of the steps for producing the semiconductor devices can be used in common to enhance the productivity. In this case, however, unnecessary circuits are inevitably formed causing the degree of integration to decrease. Besides, after either interface is selected by the metal option, the products must be managed as different products.
In order to simplify the circuit and to facilitate the management of products, the present inventors have contrived an input circuit that receives input signals having relatively large amplitudes like those of LVTTL and LVMOS as well as the signals of small amplitudes that change near a neutral-point voltage like those of the above-mentioned SSTL. In developing such an input circuit, the inventors have contrived not to permit the flow of an operation current into the input circuit when the semiconductor integrated circuit device is not in operation like in the LVTTL and LVCMOS interfaces, in addition to stably forming internal signals in response to dissimilar input signals. Further, in the input circuits such as of the above-mentioned LVTTL and LVCMOS, the present inventors have attempted to realize input/output transfer characteristics that are adapted to a low threshold voltage as the devices are realized in fine sizes, and to reduce the consumption of electric power and increase the stability.
An object of the present invention is to provide a semiconductor integrated circuit device which substantially decreases the consumption of electric power while enabling an input circuit therefor to be simplified and the management and handling of the products to be facilitted.
Another object of the present invention is to provide a semiconductor integrated circuit device equipped with an input circuit adapted to finely fabricating the devices and is capable of realizing stable input/output transfer characteristics.
The above and other objects of the present invention as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Briefly described below is a representative example of the invention disclosed in the present application. That is, an input circuit in which differential amplifier circuits that receive an input signal fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bias voltage-generating circuit when said input signal is near a central voltage between said first operation voltage and said second operation voltage, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.
Briefly described below is another representative example of the invention disclosed in the present application.
That is, an input circuit for receiving input signals fed through the external terminals, comprising:
a first differential amplifier circuit including differential MOSFETs of a first type of electric conduction and a first MOSFET of the first type of electric conduction provided for the common sources thereof to form an operation current;
a second differential amplifier circuit including differential MOSFETs of a second type of electric conduction and a second MOSFET of the second type of electric conduction provided for the common sources thereof to form an operation current; and
an inverter circuit for forming an output signal;
wherein an input signal is fed from an external terminal to the input terminals of one side of said first and second differential amplifier circuits, a reference voltage which is nearly an intermediate potential between the high level and the low level of the input signal is fed to the input terminals on the other side of said first and second differential amplifier circuits, and an output signal is synthesized from those of said first and second differential amplifier circuits which are in phase and is fed to the input terminal of said inverter circuit.
REFERENCES:
patent: 5442277 (1995-08-01), Mori et al.
patent: 5557221 (1996-09-01), Taguchi et al.
patent: 5751186 (1998-05-01), Nakao
patent: 6121812 (2000-09-01), Tsukikawa
patent: 3-219722 (1991-09-01), None
patent: 5-48430 (1993-02-01), None
patent: 6-104725 (1994-04-01), None
patent: 6-104726 (1994-04-01), None
patent: 7-7412 (1995-01-01), None
patent: 7-143184 (1995-06-01), None
patent: 7-240679 (1995-09-01), None
patent: 9-172363 (1997-06-01), None
patent: 10-173509 (1998-06-01), None
NEC Technical Report, vol. 50, No. 3, 1997, Development Technology for Third-generation 64-bit DRAM.
Morita Sadayuki
Nagashima Osamu
Ohi Masafumi
Sakata Takeshi
Tanaka Hitoshi
Hitachi , Ltd.
Le Don Phu
Mattingly Stanger & Malur, P.C.
Tokar Michael
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