Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-02-19

2002-05-07

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For high frequency device

C257S500000, C257S663000, C257S758000

Reexamination Certificate

active

06384479

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an analog circuit and a digital circuit formed on a single substrate.
2. Description of the Prior Art
An IC (integrated circuit) designed for use in an FDD (floppy disk drive) (hereafter such an IC will be referred to as an “FDD IC”) has a read/write circuit for writing and reading data to and from a floppy disk as well as a control circuit for controlling the read/write circuit. Whereas the control circuit is a digital circuit formed by logic circuits composed of CMOS (complementary metal-oxide semiconductor) devices, the read/write circuit is an analog circuit composed of bipolar transistors. Conventionally, an analog circuit and a digital circuit are arranged as separate blocks, and the control circuit and the read/write circuit are arranged next to each other.
Arranging the control circuit as a separate block in this way, however, makes it inevitable that the control circuit is given an unnecessarily large block size. This means that the wiring pattern that is laid to give the control circuit necessary functions has to cover an unnecessarily large area (i.e. the wiring has to cover an unnecessarily large area), and thus causes an unduly long delay in signal transfer (i.e. signals come to have “blunt” rising and trailing edges). As a result, unless the CMOS devices forming the control circuit have an extremely high driving capacity, it is not possible to secure a sufficient margin for the operation speed of the control circuit (in particular, the high-frequency handling portion thereof). This makes it impossible to achieve a satisfactorily high yield of an FDD IC, and thereby makes the costs of the FDD IC, and thus the costs of the FDD apparatus employing it, unnecessarily high.
Moreover, a long delay in signal transfer reduces the switching speed of the CMOS devices forming the control circuit, and thereby lengthens the period in which through currents flow through the CMOS devices. This leads to unduly high power consumption.
The control circuit includes, as its internal circuits, a circuit that handles high-frequency signals (hereafter such a circuit will be referred to as a “high-frequency” circuit) and a circuit that handles low-frequency signals (hereafter such a circuit will be referred to as a “low-frequency” circuit). Since the control circuit is conventionally arranged as one block, the read/write circuit, which is an analog circuit, has to be arranged next to the high-frequency circuit provided within the control circuit. The problem here is that the operation of the high-frequency circuit causes noise that degenerates the operation characteristics of an analog circuit. For this reason, conventionally, a guard ring is provided between the control circuit and the read/write circuit to buffer such noise (specifically, as large a gap as possible is secured between the control circuit and the read/write circuit). This, however, leads to a reduced circuit density, an increased chip area, and increased costs of the FDD IC, and thus makes the size and the costs of the FDD apparatus employing it even higher.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device that allows redundancy in a low-frequency circuit included in a digital circuit provided therein, that operates with lower power consumption, and that can be manufactured with a smaller circuit area and at lower costs.
To achieve the above object, according to the present invention, in a semiconductor integrated circuit device having an analog circuit and a digital circuit formed as separated blocks on a single substrate and having a plurality of conductor layers, a high-frequency circuit belonging to the digital circuit that handles signals of relatively high frequencies and a low-frequency circuit belonging to the digital circuit that handles signals of relatively low frequencies are arranged as separate blocks, and in addition the wiring of the low-frequency circuit is achieved without using particular one or ones of the conductor layers.
Here, arranging the high-frequency and low-frequency circuits as separate blocks helps reduce the area that needs to be covered by a wiring pattern in each circuit so as to give the circuit necessary functions, and thus helps minimize the delay in signal transfer that occurs in each circuit. In addition, the high-frequency and low-frequency circuits, when arranged as separate blocks, are allowed to use the conductor layers in different ways.
Thus, in the above-described configuration according to the present invention, the low-frequency circuit is given necessary functions by being wired without using particular one or ones of the conductor layers provided. This makes it possible to alter the wiring by using the particular one or ones of the conductor layers that were previously left unused.
Note that the greater the number of conductor layers that are used to give circuits their respective functions, the shorter the individual wiring paths, and thus the shorter the delay in signal transfer. That is, the low-frequency circuit is affected less seriously by the delay in signal transfer than the high-frequency circuit is. Therefore, with the low-frequency circuit, it is advisable to give priority to securing as much redundancy as possible rather than to minimizing the delay in signal transfer. On the other hand, with the high-frequency circuit, to which the delay in signal transfer does more harm than redundancy does good, it is advisable to design the wiring pattern in such a way as to minimize the delay in signal transfer at the cost of redundancy.
A shorter delay in signal transfer helps increase the switching speed of the CMOS devices forming the digital circuit, and thereby shorten the period in which through currents flow through the CMOS devices.
Moreover, arranging the high-frequency and low-frequency circuits of the digital circuit as separate blocks helps reduce the space that needs to be secured as a guard ring between the analog circuit and the high-frequency circuit to buffer noise.
Furthermore, arranging the low-frequency circuit between the high-frequency circuit and the analog circuit helps make the analog circuit less susceptible to the noise resulting from the operation of the high-frequency circuit.


REFERENCES:
patent: 5773887 (1998-06-01), Pavio et al.
patent: 5841197 (1998-11-01), Adamic, Jr.
patent: 5939755 (1999-08-01), Takeuchi et al.
patent: 5994759 (1999-11-01), Darmawan et al.
patent: 6072223 (2000-06-01), Noble

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2820286