Semiconductor integrated circuit device

Static information storage and retrieval – Systems using particular element – Multiaperture cell

Reexamination Certificate

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C365S145000, C257S202000

Reexamination Certificate

active

07379319

ABSTRACT:
A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate.

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Daisaburo Takashima, et al., “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM)”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 787-792.
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Shigeo Onishi, et al., “A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure”, IEDM, Dec. 1994, pp. 843-846.

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