Semiconductor integrated circuit device

Static information storage and retrieval – Read/write circuit – Differential sensing

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36518901, 357 236, G11C 1140, G11C 1300

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active

049673963

ABSTRACT:
The present invention relates to a dynamic type RAM and, more particularly, to a dynamic type RAM formed using one-element type dynamic memory cells each comprised of a data storing capacitor and an address selecting MOSFET. Divided word lines are arranged such that one divided word line intersects another at a point of discontinuity of the other divided word line adjacent to a joint of the one divided word line to the corresponding word line. This prevents generation of an array noise due to coupling capacitances, and thus improves the read margin.

REFERENCES:
patent: 4733374 (1988-03-01), Furuyama et al.
patent: 4750026 (1988-06-01), Kuninobu et al.
patent: 4792841 (1988-12-01), Nagasawa et al.
patent: 4809046 (1989-02-01), Aoyama et al.
"A 90ns 256K x 1b DRAM with Double Level Al Technology", Fujii et al., 1983, IEEE ISSCC, Feb. 25, 1983, pp. 226-227.

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