Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-03-06
2001-11-27
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
Reexamination Certificate
active
06324104
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, namely a semiconductor integrated circuit device which has a main storage portion, and an auxiliary storage portion functioning as a cache memory, formed on the same semiconductor substrate, and a data transfer circuit between the main storage portion and the auxiliary storage portion. In particular the invention relates to a redundant configuration for saving defects of the auxiliary storage portion.
2. Description of the Related Art
In general, a relatively low speed low cost and large capacity semiconductor device is used as the main storage device used in a computer system. As a device which meets these requirements, a general purpose DRAM is generally used.
Moreover, with recent computer systems speeding up of the DRAM constituting the main storage portion has resulted to meet the higher speed of systems (in particular the higher speed of the MPU). However this is found to be insufficient to meet the higher speed of the MPU, and the main trend is for a system where a high speed memory is mounted as an auxiliary storage portion between the MPU and the main storage portion. Such an auxiliary storage portion is generally referred to as a cache memory, and uses for example a high speed SRAM, or a EDRAM.
As a mounting configuration for a cache memory, in general there is a configuration where this is mounted outside of the MPU, or a configuration where this is built into the MPU. Recently however a semiconductor memory device where a DRAM constituting the main storage portion, and a cache memory are mounted on the same semiconductor substrate, is gaining attention. As this conventional technology, there is for example Japanese Patent Application, First Publication Nos. Sho. 57-20983, 60-7690, 62-38590, and Japanese Patent Application, First Publication No. Hei. 1-146187. With the semiconductor memory devices of this prior art, the DRAM and the cache memory are mounted on the same substrate and hence overall this is referred to as a cache DRAM. Moreover this is also described as a CDRAM. These give a configuration where data can be transferred both ways between a SCRAM which functions as a cache memory, and the DRAM which constitutes the main storage portion.
In these prior arts, there are problems such as a delay in the operation of the data transfer at the time of a cache mis hit, and hence an improved technology is proposed. For the improved conventional technology there is the following. For example with the technology related to Japanese Patent Application, First Publication Nos. Hei. 4-252486, 4-318389, and 5-2872, a feature is that a latch or a register function is provided in a two way data transfer circuit for performing data transfer between a DRAM portion and a SCRAM portion, so that data transfer from the SCRAM portion to the DRAM portion, and data transfer from the DRAM portion to the SCRAM portion can be performed simultaneously. Hence data transfer at the time of a cache mis hit, (copy back) can be speeded up.
However, in the above-mentioned conventional technology, the occupied area of the two way transfer gate circuit becomes large so that the number of circuits which can be installed is limited. As a result the number of transfer bus lines is also limited. Therefore, the number of bits which can be transferred at a time between the DRAM array and the SCRAM array is limited to 16 bits. In general, the smaller the number of bits which can be transferred at a time, the lower the cache hit ratio.
Furthermore, recently, there is a problem of a drop in the cache hit ratio for the case where an access request is received from a plurality of processing units as shown in FIG.
86
. In the case where an access request is received from a plurality of processing units (memory masters), the requesting of addresses of different sets (rows) increases. In this case, if the abovementioned CDRAM or EDRAM is used for the main memory of
FIG. 86
, then the cache hit ratio drops, and the speeding up of the overall system is limited. With the increase of systems having this plurality of processing units (memory masters), then the memory portion also, rather than being the conventional device which corresponds mainly to one type of access request, must be one which can correspond to multiple types of access requests.
Furthermore, with recent miniaturization, the frequency of the occurrence of defects in the memory cell region increases. Therefore, with a DRAM portion constituting a main storage portion of large storage capacity, it is common to provide a redundant circuit for saving defective bits. However, even if the defective bits of the main storage portion are saved, if defects in the auxiliary storage portion which functions as a cache memory cannot be saved, then the defect saving in the main storage portion is in vain,
Moreover, with the speeding up of read speed, it is necessary to avoid reduction in the read speed accompanying defect saving.
SUMMARY OF THE INVENTION
The present invention addresses the abovementioned situation with the object of providing a semiconductor integrated circuit device which can quickly deal with an access request from a plurality of memory masters without a drop in cache hit ratio, and which can save defects of an auxiliary memory portion functioning as a cache memory without an accompanying drop in read speed.
In order to solve the abovementioned problems, the present invention has the following configuration.
That is to say, the semiconductor integrated circuit device of the present invention according to a first aspect has a main storage portion (for example a component corresponding to a later mentioned DRAM portion
101
), and an auxiliary storage portion (for example a component corresponding to a later mentioned SRAM portion
102
) functioning as a cache memory, and is constructed such that two way data transfer is possible between the main storage portion and the auxiliary storage portion, and the auxiliary storage portion is provided with, a normal memory cell array (for example a component corresponding to a later mentioned common SRAM array MA) with memory cells which are alternatively selected based on a selection signal, arranged in matrix form, and a redundant memory cell array (for example a component corresponding to a later mentioned redundant SCRAM array MAR) provided adjacent to the memory cell array with the position of rows matching, and with redundant memory cells which are alternatively selected based on a redundant selection signal, arranged in matrix form, and a plurality of auxiliary data lines (for example components corresponding to later mentioned redundant data input/output lines SIOR, and normal data input/output lines SIO) to which memory cell groups of each row are connected are separately provided in the normal memory cell array and the redundant memory cell array.
Moreover, the semiconductor integrated circuit device of the present invention according to a second aspect has a main storage portion (for example a component corresponding to a later mentioned DRAM portion
101
), and an auxiliary storage portion for example a component corresponding to a later mentioned SRAM portion
102
) functioning as a cache memory, and is constructed such that two way data transfer is possible between the main storage portion and the auxiliary storage portion, and the auxiliary storage portion is provided with, a memory cell array (for example a component corresponding to a later mentioned common SRAM array MA) with memory cells which are alternatively selected based on a selection signal (for example an element corresponding to a later mentioned read/write SRAM row selection signal and SRAM column selection signal), arranged in matrix form, a plurality of auxiliary data lines (for example components corresponding to later mentioned common data input/output lines SIO) provided along rows of the memory cell array, to which memory cell groups belonging to each row of the memory cell array are connect
NEC Corporation
Phung Anh
Sughrue Mion Zinn Macpeak & Seas, PLLC
Zarabian Amir
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