Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-11-15

2001-05-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06229741

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device provided with a test circuit and a redundant circuit for a memory circuit section.
2. Description of the Related Art
A conventional test circuit and redundant circuit for a storage circuit portion in a semiconductor integrated circuit device is disclosed, for instance, in a U.S. Patent document U.S. Pat. No. 5,815,512 (corresponding to a Japanese laid open publication No. JP-A-8/94718).
FIG. 1
is a circuit diagram depicting a conventional scan flip-flop (SFF) for testing a memory circuit such as a RAM (a Random Access Memory). In
FIG. 1
, Reference numeral
211
designates a scan flip-flop and
212
denotes a comparator incorporated therein. The comparator
212
compares the output from the RAM as the memory circuit with an expected value and then outputs a comparison result. Reference numeral
213
denotes a flip-flop (FF) for holding the comparison result provided from the comparator
212
.
FIG. 2
is a block diagram showing a memory circuit such as a RAM equipped with a conventional test circuit. In
FIG. 22
, Reference numeral
221
designates the RAM as a memory circuit, and
211
denotes four denotes flip-flops, which are connected in series to form a scan path for testing the RAM
221
. The scan flip-flops
211
are each identical in construction to that depicted in FIG.
21
.
Next, a description will be given of the operation of the RAM
221
equipped with the conventional test circuit.
The RAM
221
equipped with the conventional test circuit, depicted in
FIG. 22
, provides data output signals DO<
0
>, DO<
1
>, DO<
2
> and DO<
3
> of four bits to the scan flip-flops
211
forming the scan paths respectively corresponding thereto.
The RAM
221
is tested following the procedure described below.
First, the procedure begins with setting control signals TM and SM at 0 and 1, respectively (TM=0 and SM=1), prior to the start of the test. Then a signal SIDO=1 is input into the uppermost scan flip-flop
211
.
The prior art example shown in
FIG. 2
has the four series-connected scan flip-flops
211
, and hence it requires four clocks to set the value
1
in all of them. Accordingly, the scan flip-flops
211
output signals SO<
0
>=1, SO<
1
>=1, SO<
2
>=1, and SO<
3
>=1, respectively.
The next step is to set the control signals TM and SM both at 1 (TM=1 and SM=1). This is followed by testing the RAM
221
at every address. That is, the test is carried out by writing test data in and reading out of the RAM
221
while at the same time appropriately controlling an expected value EXP and a comparison control signal CMP (which indicates a comparison when it is 1).
If there is a defect in the RAM
221
, the output DO<> from the RAM
221
differs from the expected value EXP, and the output from a comparator (
212
in
FIG. 21
) in the corresponding scan flip-flop
211
goes to zero, and this scan flip-flop
211
is reset to 0 in synchronization with the clock signal T.
For instance, when a fault is detected in the scan flip-flop
211
(SFF<
2
>) corresponding to the output DO<
2
> from the RAM
221
, the output signal SO<
2
> from that scan flip-flop goes to 0. The output signals from the other scan flip-flops, however, remain unchanged, i.e. SO<
0
>=1, SO<
1
>=1, and SO<
3
>=1.
Next, the control signals TM and SM are set at 0 and 1, respectively (TM=0 and SM=1), followed by shifting out the test results SODO<
0
> from the last-stage scan flip-flop
211
.
FIG.3
is a block diagram showing a conventional memory circuit such as a RAM equipped with a test circuit and a redundant circuit. In
FIG. 3
, Reference numeral
231
designates a RAM provided with the test circuit shown in
FIG. 2
,
232
denotes a redundant circuit, and
233
denotes a register for temporarily storing the outputs from the scan flip-flops.
In the configuration shown in
FIG. 3
, the redundant circuit
232
is incorporated in the RAM with the test circuit shown in FIG.
2
. For example, when a failure is detected based on the output SFF<
2
> from the scan flip-flop corresponding to the output DO<
2
> from the RAM as a memory circuit, the signal SO<
2
> goes to 0 (SO<
2
>=0). On the other hand, the outputs SO<
0
> SO<
1
> and SO<
3
> from the other scan flip-flops each remain at 1 (SO<
0
>=1 SO<
1
>=1, and SO<
3
>=1).
When the register
233
stores these signals SO<> are, the signals G<
1
>=1, G<
2
>=0 and G<
3
>=1 are provided, and these signals G<> become F<
3
>=1, F<
2
>=0 and F<
1
>=0, respectively. As a result, signals DO<
3
>/Q<
3
>, DO<
1
>/Q<
1
> and DO<
0
>/Q<
0
> are transferred as signals XDO<
2
>, XDO<
1
> and XDO<
0
>, respectively, and the signal DO<
2
> provided from the failing portion in the RAM
231
is not transferred to the outside. Similarly, input data signals XDI<
2
>, XDI<
1
>, and XDI<
0
> from the outside are transferred to the RAM
23
l as signals DI<
3
>, DI<
2
>, DI<
1
>, and DI<
0
> shown in FIG.
3
.
Based on the switching operation for switching the output from the defective memory cell to the output from the redundant circuit described above, the normal operation of a 3-bit input/output RAM can be performed correctly even if there is a fault of a memory circuit in the RAM
231
corresponding to the signal DO<
2
>. However, there is a drawback that it is difficult to repair defective memory cells if the data output signals DO<> indicate that the RAM includes two or more defective bits.
Because of such a configuration as described above, the conventional semiconductor integrated circuit device equipped with the test circuit and the redundant circuit has, for its data input/output (data I/O), an additional memory cell corresponding to one bit for self-repairing use. That is, it is necessary to use a RAM that has an extra memory cell corresponding to the one-bit input/output. Hence, this technique cannot be applied to the semiconductor integrated circuit device once the RAM layout design is completed. Its application requires a redesign of the RAM and hence takes much time. The prior art has another problem that the incorporation of the redundant circuit inevitably increases the number of memory cells corresponding to the number of words of the RAM involved.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor integrated circuit device equipped with a test circuit and a redundant circuit wherein the redundant circuit for redundant bits is formed by using another RAM that is not a RAM as a memory circuit, thereby making unnecessary design changes in the layout of the RAM forming the memory circuit in the semiconductor integrated circuit device.
A further object of the present invention is to provide a semiconductor integrated circuit permitting reduction of the number of memory cells for the redundant circuit.
In accordance with one aspect of the present invention, a semiconductor integrated circuit device has a first memory circuit, a second memory circuit, and a redundancy control circuit. The first memory circuit has an address decoder and at least first and second memory cell groups, each memory cell group includes memory cells of a number corresponding to the number of words, and which outputs first and second data from the first and second memory cell groups. The second memory circuit has an address decoder and a third memory cell group including memory cells of a number smaller than or equal to the number of words of the first memory circuit and outputs third data from said third memory cell group. The redundancy control ci

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