Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1998-03-24

2001-04-10

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C327S544000

Reexamination Certificate

active

06215159

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with a CMOS logic circuit capable of securely carrying out ON/OFF control of MOS transistor for controlling current in the stand-by state even if the power supply voltage is lowered.
A conventional MT-CMOS circuit (Multi Threshold-CMOS circuit) is shown in FIG.
20
.
As shown in
FIG. 20
, the conventional semiconductor integrated circuit device includes a CMOS logic circuit CM, and a P-channel MOS transistor MP
2
for controlling current in stand-by state.
Hitherto, the MT-CMOS circuit is caused to be operative at a low voltage for the purpose of realization of low power consumption. For this reason, P-channel MOS transistor MP
1
and N-channel MOS transistor MN
1
, etc. forming the CMOS logic circuit CM are caused to have low threshold value to suppress delay of propagation of signal at the logic gate. For example, the threshold value of the P-channel MOS transistor MP
1
is caused to be −0.2 V and the threshold value of the N-channel MOS transistor MN
1
is caused to be 0.2V, etc.
However, even with the circuit configuration including MOS transistors of low threshold value, there results in an increased value of leakage current also in the state where the circuit operation is halted (stand-by state). This cannot be disregarded. In view of the above, there was employed a configuration in which P-channel MOS transistor MP
2
of high threshold value (e.g., −0.7 V, etc.) is inserted between the power supply line and the MOS transistors of low threshold value constituting the CMOS logic circuit. Further, the P-channel MOS transistor MP
2
was turned OFF by applying the same voltage as the power supply voltage VDD to its gate in the stand-by state to thereby reduce such leakage current. On the other hand, the P-channel MOS transistor MP
2
was turned ON by applying 0V to its gate in the operating state to thereby deliver power supply voltage VDD to the CMOS logic circuit (see, e.g., “1V operation MTCMOS DSP employing low voltage applicable power control mechanism” (particularly “MTCMOS circuit” of
FIG. 2
) by Mr. Shinichiro Mutoh et al., NTT LSI Research Institute, Technical Report of the Institute of Electronics and Communication Engineering of Japan, Vol. 96, No. 107, pp. 15-20, Technical Research Report of the Institute of the Electronic Information and Communication of Japan).
However, in the prior art, there are problems as described below. Namely, at the time of stand-by state of MT-CMOS, power supply voltage VDD is applied to the source of the P-channel MOS transistor MP
2
for reducing leakage current and 0V which is low level is applied to the gate. Therefore, as the gate-source voltage VGS of the P-channel MOS transistor MP
2
, as far as VDD is only applied even at the maximum. Accordingly, when the P-channel MOS transistor MP
2
is caused to be operative at a low voltage such that the power supply voltage and the threshold value of the transistor are close to each other, it cannot be sufficiently turned ON.
In such a case, the channel width must be enlarged in order to lower ON resistance of the P-channel MOS transistor MP
2
. As a result, the chip area is increased. Moreover, when the power supply voltage is caused to be less than the threshold value of the P-channel MOS transistor MP
2
, it becomes difficult to allow this transistor to be operative. It is the premise that transistor of high threshold value is used as the P-channel MOS transistor MP
2
so that leakage current sufficiently becomes small when it is caused to be turned OFF at the time of stand-by (stand-by state) for the purpose of reducing leakage current in the stand-by state. Accordingly, when the threshold value is assumed to be −0.7 V, the minimum power supply voltage from a viewpoint of practical use is considered to be about 1V (the variable range of the threshold value is assumed to be −0.7 V±0.1 V, and the change in the power supply voltage is assumed to be 1 V±10%). Thus, when the power supply voltage becomes equal to, e.g., 0.5 V, the operating voltage does not exceed the threshold value. As a result, ON/OFF control cannot be carried out.
As described above, in the prior art, in the case where the power supply voltage VDD is lowered, the power supply voltage and the threshold value of the MOS transistor become close to each other. As a result, ON/OFF control becomes difficult. In addition, there results increased channel width in ON state. Ultimately, the MOS transistor becomes difficult to function.
SUMMARY OF THE INVENTION
It is a principal object of this invention to apply 0V or less, or higher voltage of VDD or more in place of the conventional system in which signal of 0V-VDD is applied to the gate of the MOS transistor for controlling current in the stand-by state in the CMOS logic circuit to thereby reliably carry out ON/OFF operation of the MOS transistor for controlling current in the stand-by state even if the power supply voltage VDD is allowed to be low voltage.
It is an another object of this invention to improve reliability by using the CMOS logic circuit and the MOS transistor for controlling current in the stand-by state in the state where excessive voltage is not applied to any portion thereof.
It is a further object of this invention to provide a semiconductor integrated circuit device effective for realization of miniaturization and reduced withstand voltage in semiconductor integrated circuit devices in which miniaturization thereof has been developed and withstand voltage has a tendency to be lowered.
In accordance with this invention, an approach is employed to apply 0V or less, or higher voltage of VDD or more to the gate of the MOS transistor for controlling current in the stand-by state in the CMOS logic circuit in place of the conventional system of applying signal of 0V-VDD thereto, thereby permitting the MOS transistor for controlling current in the stand-by state to reliably carry out ON/OFF operation even if the power supply voltage VDD is caused to be low voltage. Thus, increase in the channel width of MOS transistors constituting the circuit can be prevented. Further, since the circuit can be constituted by MOS transistors all having the same low threshold value, the process can be simplified.
Moreover, in the case where CMOS signal logic circuit is used at the preceding stage of the CMOS logic circuit, signal from another power supply logic circuit is delivered to this CMOS logic circuit. As a result, level conversion circuit becomes unnecessary. Thus, the circuit can be simplified and the area can be reduced.
Further, since there is employed a configuration in which plural MOS transistors for controlling current in the stand-by state are connected in series, the CMOS logic circuit and the MOS transistor for controlling current in the stand-by state can be used in the state where excessive voltage is not applied to any portion thereof. Accordingly, employment of this circuit configuration is extremely effective for improvement in reliability.
Further, in the semiconductor integrated circuit device in which miniaturization of the semiconductor integrated circuit device has been developed and the withstand voltage has a tendency to be lowered, this invention provides conspicuous advantages in realization thereof.
In addition, since the semiconductor integrated circuit device of this invention is of the low power consumption type, such semiconductor integrated circuit device is applied to battery driven equipments including portable equipments, e.g., PDA, PHS, pocket (portable) telephone, etc., thereby making it possible to exhibit extremely conspicuous advantages.


REFERENCES:
patent: 6016281 (2000-01-01), Brrox
patent: 6034563 (2000-03-01), Mashiko
Mutoh et al., “A 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Applications,” IEEE International Solid State Circuits Conference, pp. 168-169, 438, 1996.*

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