Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-07-21
2001-04-17
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S309000, C327S433000, C327S438000
Reexamination Certificate
active
06218881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as an LSI (large-scale integrated circuit).
2. Description of the Prior Art
In a semiconductor integrated circuit device such as an LSI, the output circuit constituting a part of each I/O cell is typically formed in a CMOS structure. Such output circuits may suffer electrostatic destruction when fed with abnormal electrostatic charge by way of their output terminal from the outside, and therefore they are usually provided with a protection circuit against static electricity.
In a conventional example shown in
FIG. 5
, a P-channel MOS transistor
101
and an N-channel MOS transistor
102
are connected between a power source line
106
and ground GND, with their gates connected to an input terminal
100
and their drains connected to an output terminal
103
. In addition, diodes
104
and
105
are provided for protection. The diode
104
is turned on when abnormal positive electrostatic charge is applied to the output terminal
103
from the outside, so that the electrostatic charge is bypassed to the power source line
106
. Meanwhile, the diode
105
remains off.
The diode
105
is turned on when abnormal negative electrostatic charge is applied to the output terminal
103
, so that a current flows from ground to the output terminal
103
to discharge the electrostatic charge at the output terminal
103
. These diodes
104
and
105
are, conventionally, formed separately from the transistors
101
and
102
on a semiconductor substrate.
In
FIG. 6
, blocks
111
and
112
are formed on a single semiconductor substrate. The block
111
includes a P-channel MOS transistor
101
and a diode
104
, and the block
112
includes an N-channel MOS transistor
102
and a diode
105
. The drains of the transistors
101
and
102
, the anode of the diode
104
, and the cathode of the diode
105
are connected together with a wire
107
.
It is a well-known disadvantage of this type of output circuit that the CMOS transistors form parasitic bipolar transistors that act as thyristors. Such parasitic transistors cause a condition called “latchup”, and thereby induce malfunctioning of the CMOS transistors.
To avoid the formation of such parasitic transistors that act as thyristors, it has been customary to secure a sufficient interval
108
between adjacent blocks ill and
112
. On the other hand, the protection provided by the protection circuit composed simply of diodes
104
and
105
has been insufficient to cope with extremely high electrostatic charge applied to the output circuit
103
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device that is highly reliable by being securely protected against electrostatic charge.
Another object of the present invention is to provide a semiconductor integrated circuit device that is securely protected against electrostatic charge without unduly increasing the space for output circuits.
To achieve the above objects, according to one aspect of the present invention, a semiconductor integrated circuit device having an output circuit of a CMOS structure type composed of a P-channel MOS transistor that has its gate connected to an input terminal, has its source connected to a power source line, and has its drain connected to an output terminal and an N-channel MOS transistor that has its gate connected to the input terminal, has its source connected to ground, and has its drain connected to the output terminal is further provided with: a first protection diode formed in parallel with the source-drain channel of the P-chaninel MOS transistor; a first NPN-type transistor formed so that its base is connected to ground and its collector-emitter path is connected in parallel with the source-drain channel of the P-channel MOS transistor; a second protection diode formed in parallel with the source-drain channel of the N-channel MOS transistor; and a thyristor circuit formed in parallel with the source-drain channel of the N-channel MOS transistor and operating only when abnormal electrostatic charge is applied to the output terminal.
In this structure, for example, the first protection diode and the thyristor circuit are turned on when abnormal positive electrostatic charge is applied to the output terminal, and, for example, the second protection diode and the first NPN-type transistor are turned on when abnormal negative electrostatic charge is applied to the output terminal. Thus, not only the protection diodes but also the first NPN-type transistor and the thyristor circuit are turned on to discharge the electrostatic charge, and this helps improve the resistance to electrostatic charge accordingly.
Moreover, according to another aspect of the present invention, the first protection diode and the thyristor circuit are formed between the P-channel MOS transistor and the N-channel MOS transistor on a semiconductor substrate.
In a conventional CMOS-type output circuit, a P-channel MOS transistor and an N-channel MOS transistor are formed with a sufficient interval between them to suppress the action of a parasitically formed thyristor circuit. By contrast, according to the present invention, such a parasitically formed thyristor circuit is used intentionally as a protection circuit, and therefore there is no need to unduly increase the chip area.
Moreover, according to another aspect of the present invention, the thyristor circuit is composed of a PNP-type transistor that has its base connected to the power source line, has its emitter connected to the output terminal, and has its collector connected through a resistor to ground and a second NPN-type transistor that has its base connected to the resistor, has its collector connected to the base of the PNP-type transistor, and has its emitter connected to ground.
Since the second NPN-type transistor has its base connected through the resistor to ground, its base voltage is stably kept at the ground level, and therefore it is never turned on under normal conditions. Even if the PNP-type transistor is turned on, its output current is so low that the voltage appearing across the resistor and thus applied to the base of the second NPN-type transistor is too low to reach the threshold voltage of this transistor.
Moreover, according to another aspect of the present invention, the first protection diode is formed between an N well formed in a P
−
substrate and a P
+
region formed within the N well. The PNP-type transistor of the thyristor circuit is formed as a parasitic transistor by the P
+
region, the N well, and the P
−
substrate. The second NPN-type transistor of the thyristor circuit is formed as a parasitic transistor by the source region of the N-channel MOS transistor, the P
−
substrate, and the N well.
That is, both the PNP-type transistor and the second NPN-type transistor constituting the thyristor are formed as parasitic transistors by the use of the N well, the P
+
region, and others that serve to form the first protection diode. This helps minimize the space required to form the protection diode and the thyristor circuit.
According to still another aspect of the present invention, the second protection diode is formed between a second P
+
region and an N
+
region formed in the P
−
substrate, and the first NPN-type transistor is formed as a parasitic transistor by the second P
+
region, the N
+
region, and the N well for the P-channel MOS transistor.
REFERENCES:
patent: 4066915 (1978-01-01), Ohhinata
patent: 4678933 (1987-07-01), Pedone
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 5734541 (1998-03-01), Iniewski et al.
Arent Fox Kintner & Plotkin & Kahn, PLLC
Le Dinh T.
Rohm & Co., Ltd.
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