Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1998-03-27

2001-06-05

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C327S530000, C365S227000

Reexamination Certificate

active

06242948

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device intended to reduce its power consumption.
2. Description of the Prior Art
Recent developments in portable or mobile equipment have caused requirements of low power semiconductor integrated circuit devices, which can be built in mobile equipment, for long battery life. Reduction in the operating voltage of a semiconductor integrated circuit device is one of effective methods of reducing the power consumption. Since the power consumption is the product of the current and the voltage, both the voltage and the current can be reduced along with the reduction in the operation voltage. It is therefore said that in general, reduction in the operating voltage of a semiconductor integrated circuit device can produce a squared effect with respect to the reduction in the power consumption.
On the other hand, a MOSFET which constructs a semiconductor integrated circuit device has the property that, as the power voltage applied thereto is reduced, its performance is reduced and hence its response speed is reduced. To avoid the reduction in the performance of a MOSFET, it is necessary to reduce the threshold voltage according to the reduction in the power voltage. However, the threshold voltage cannot be reduced in proportion to the reduction in the power voltage, in practice. This is because the reduction in the threshold voltage causes an increase in the amount of a leak current flowing in a MOSFET when the MOSFET is held in its off state and hence an increase in the power consumption.
To overcome the above problem, a prior art method as disclosed in Japanese Patent Application Laying Open (KOKAI) No. 7-212218 has been used. Referring next to
FIG. 15
, there is illustrated a schematic circuit diagram of a prior art semiconductor integrated circuit device which can run from low voltage supply. The device is constructed from a multi-threshold CMOS or MT-CMOS. In the figure, reference numeral
1
denotes a two-input NAND gate,
2
and
3
denote p-channel MOSFETs,
4
and
5
denote n-channel MOSFETs,
6
denotes a p-channel MOSFET which can be turned on in response to a control signal
9
asserted LOW so as to connect a power supply
7
with a power supply line
8
(VA1), and
10
denotes an n-channel MOSFET which can be turned on in response to a control signal
13
asserted HIGH so as to connect a ground potential node or GND
11
with a power supply line
12
(VB1). The absolute values of the threshold voltages of the p-channel MOSFET
6
and the n-channel MOSFET
10
are set to be greater than those of the threshold voltages of the p-channel MOSFETs
2
and
3
and the n-channel MOSFETs
4
and
5
which construct the two-input NAND gate
1
.
Each of the p-channel MOSFETs
2
and
3
has a substrate terminal connected to the VA1
8
, and each of the n-channel MOSFETs
4
and
5
has a substrate terminal connected to the VB1
12
. The p-channel MOSFET
6
has a substrate terminal connected to the power supply
7
, and the n-channel MOSFET
10
has a substrate terminal connected to the GND
11
.
When activating the two-input NAND gate
1
as shown in
FIG. 15
, the control signal
9
is caused to make a HIGH to LOW transition and the control signal
13
which is the inversion of the control signal
9
is therefore caused to make a LOW to HIGH transition. Both the p-channel MOSFET
6
and the n-channel MOSFET
10
are then turned on, and therefore the potential of the VA1
8
rises to the potential of the power supply
7
and the potential of the VB1
12
descends to the level of the GND
11
. As a result, the two-input NAND gate
1
can operate as a normal NAND circuit. In this case, since the absolute values of the threshold voltages of the MOSFETs
2
through
5
are set to be relatively small, the NAND gate
1
runs at a high speed even though the voltage from the power supply
7
is low.
When deactivating the two-input NAND gate
1
, the control signal
9
is caused to make a LOW to HIGH transition and the control signal
13
which is the inversion of the control signal
9
is therefore caused to make a HIGH to LOW transition. Both the p-channel MOSFET
6
and the n-channel MOSFET
10
are then turned off and therefore the VA1
8
and the VB1
12
are disconnected from the power supply
7
and the GND
11
, respectively. Since the absolute values of the threshold voltages of the p-channel MOSFET
6
and the n-channel MOSFET
10
are set to be greater than those of the threshold voltages of the p-channel MOSFETs
2
and
3
and the n-channel MOSFETs
4
and
5
, the amounts of leak currents flowing through the MOSFETs in the two-input NAND gate
1
can be controlled to small ones.
In general, when the voltage between the gate and the source of a MOSFET is less than or equal to its threshold voltage, the leak current that flows between the source and the gate of the MOSFET increases exponentially with an increase in the gate voltage. Therefore, making a difference between the threshold voltages of the MOSFETs
2
through
5
and those of the MOSFETs
6
and
10
can reduce the leak currents flowing through the two-input NAND gate
1
not in active use by a large amount. A similar explanation can be made for any other type of internal circuitry having any size such as a logic circuit or a storage circuit, included in a semiconductor integrated circuit device, other than the two-input NAND gate
1
shown as an example of the internal circuitry.
A problem with such a prior art semiconductor integrated circuit device which can run from low voltage supply is that when the internal circuitry included in the semiconductor integrated circuit device is a combinational circuit in which its output is determined by a combination of inputs, such as a two-input NAND gate as mentioned above, the internal circuitry works properly, but,. when the internal circuitry is a sequential circuit such as a latch circuit in which its output depends on previous input conditions, there is a possibility that the internal circuitry fails to work properly, as will be explained below.
Referring next to
FIG. 16
, there is illustrated a schematic circuit diagram showing another prior art semiconductor integrated circuit device including internal circuitry which serves as a sequential circuit. The semiconductor integrated circuit device is so-called a latch circuit in which the inputs and outputs of two inverters are connected to each other while the connections cross each other. In the figure, reference numeral
20
denotes a latch circuit,
21
and
22
denote p-channel MOSFETs, and
23
and
24
denote n-channel MOSFETs. The other structure of the semiconductor integrated circuit device is the same as that of the semiconductor integrated circuit device shown in FIG.
15
. The absolute values of the threshold voltages of the p-channel MOSFET
6
and the n-channel MOSFET
10
are set to be greater than those of the p-channel MOSFETs
21
and
22
and the n-channel MOSFETs
23
and
24
which construct the latch circuit
20
.
As shown in
FIG. 16
, the latch circuit
20
is constructed of the p-channel MOSFETs
21
and
22
and the n-channel MOSFETs
23
and
24
having their threshold voltages which are relatively small. A node
25
and a node
26
pair up with each other. When one of the pair of nodes
25
and
26
is held in a HIGH logic level, the other one of the pair is held in a LOW logic level.
When a control signal
9
asserted LOW and a control signal
13
asserted HIGH are applied to the p-channel MOSFET
6
and the n-channel MOSFET
10
, respectively, the latch circuit
20
is activated. Then the nodes
25
and
26
can hold values normally. Data can be written into or read out of
25
the nodes
25
and
26
at a high speed because the absolute values of the threshold voltages of the p-channel MOSFETs
21
and
22
and the n-channel MOSFETs
23
and
24
are relatively small. However, if an attempt is made to reduce leakage currents flowing through the MOSFETs when the latch circ

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