Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-07-06

2001-01-23

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S017000, C326S083000, C326S121000, C327S534000

Reexamination Certificate

active

06177811

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a logical gate including MOS transistors.
2. Description of the Related Art
In recent years, the degrees of integration of semiconductor integrated circuits have been considerably raised, thus resulting in gigabit-class semiconductor memories being provided with several hundred millions of semiconductor devices integrated on one chip thereof and 64 bit microprocessors being provided with millions to ten millions of semiconductor devices integrated on one chip thereof. Each of the foregoing semiconductor memory and the microprocessor of the foregoing type is composed of, as well as a memory cell for storing information, a logical gate for performing logic operations.
FIG. 1A
shows a dual-input NAND gate which is a representative logical gate. The logical gate is composed of four elements consisting of two nMOS transistors M
1
and M
2
and two pMOS transistors M
3
and M
4
. Specifically, the nMOS transistor M
1
has a drain connected to output terminal Y, a gate connected to input signal XA, a source connected to node N and a substrate connected to a ground terminal Vss. The nMOS transistor M
2
has a drain connected to the node N, a gate connected to input signal XB, a source and a substrate respectively connected to the ground terminal Vss. The pMOS transistor M
3
has a drain connected to the output terminal Y, a gate connected to the input signal XA, a source and a substrate respectively connected to power supply terminal Vcc. The pMOS transistor M
4
has a drain connected to the output terminal Y, a gate connected to the input signal XB, a source and a substrate respectively connected to the power supply terminal Vcc.
FIG. 1B
is a truth table showing the logic of the foregoing logical gate. A definition is performed here that logic 0 is realized when each of input and output signals has ground potential Vss, and logic 1 is realized when the same has supply voltage Vcc. When both of the input signals XA and XB are logic 1, both of the nMOS transistors M
1
and M
2
are conductive. On the other hand, both of the pMOS transistors M
3
and M
4
are non-conductive. As a result, output Y is brought to logic 0. If at least either of the input signal XA or the input signal XB is logic 0, the nMOS transistor, to which logic 0 is supplied, is made to be non-conductive. On the other hand, the pMOS transistor, to which logic 0 is supplied, is made to be conductive. As a result, the output Y is made to be logic 1.
FIG. 2A
shows a dual-input NOR gate. Similarly to the NAND gate, the foregoing logical gate is composed of four elements consisting of two nMOS transistors M
1
and M
2
and two pMOS transistors M
3
and M
4
. Specifically, the nMOS transistor M
1
has a drain connected to output terminal Y, a gate connected to input signal XA, a source and a substrate respectively connected to ground terminal Vss. The nMOS transistor M
2
has a drain connected to the output terminal Y, a gate connected to input signal XB, a source and a substrate respectively connected to the ground terminal Vss. The pMOS transistor M
3
has a drain connected to node N, a gate connected to the input signal XA, a source and a substrate respectively connected to power supply terminal Vcc. The pMOS transistor M
4
has a drain connected to the output terminal Y, a gate connected to the input signal XB, a source connected to the node N and the substrate connected to the power supply terminal Vcc.
FIG. 2B
is a truth table showing the logic of the foregoing logical gate. When both of the input signals XA and XB are logic 0, both of the pMOS transistors M
3
and M
4
are conductive. On the other hand, both of the nMOS transistors M
1
and M
2
are non-conductive. As a result, the output Y is logic 1. When at least either of the input signals XA and XB is logic 1, the pMOS transistor, to which logic 1 is supplied, is made to be non-conductive. On the other hand, the nMOS transistor, to which logic 1 is supplied, is made to be conductive. As a result, the output Y is made to be logic 0.
FIG. 3A
shows a dual-input AND gate. The foregoing logical gate is composed of 6 elements consisting of four MOS transistors M
1
, M
2
, M
3
and M
4
forming a NAND gate, and a nMOS transistor M
5
and a pMOS transistor M
6
forming an inverter. Since the NAND gate consisting of the MOS transistors M
1
to M
4
has the same structure as that shown in
FIG. 1A
, an explanation of the operation of the NAND gate is omitted. The nMOS transistor M
5
has a drain connected to output terminal /Y, a gate connected to output terminal Y of the NAND gate, a source and a substrate respectively connected to ground terminal Vss. The pMOS transistor M
6
has a drain connected to the output terminal /Y, a source and a substrate respectively connected to the power supply terminal Vcc.
FIG. 3B
is a truth table showing the logic of the foregoing logical gate. Since an inverted signal of the NAND gate is transmitted from the foregoing logical gate, output terminal /Y is made to be logic 1 when both of the input signals XA and XB are logic 1. When at least either of the input signals XA or XB is logic 0, logic 0 is transmitted.
FIG. 4A
shows a dual-input OR gate. The foregoing logical gate is composed of 6 elements consisting of four MOS transistors M
1
, M
2
, M
3
and M
4
forming a NOR gate and a nMOS transistor M
5
and a pMOS transistor M
6
forming an inverter. Since the NOR gate consisting of the MOS transistors M
1
to M
4
is the same as that shown in
FIG. 2A
, an explanation of the operation of the NOR gate is omitted. The drain of the nMOS transistor M
5
is connected to output terminal /Y, the gate of the same is connected to output terminal Y of the NOR gate, and the source and the substrate are connected to ground terminal Vss. The drain of the pMOS transistor M
6
is connected to the output terminal /Y, the gate of the same is connected to the output terminal Y of the NOR gate, and the source and the substrate respectively are connected to the power supply terminal Vcc.
FIG. 4B
is a truth table showing the logic of the foregoing logical gate. Since an inverted signal of the NOR gate is transmitted from the foregoing logical gate, the output terminal /Y is made to be logic 0 when both of the input signals XA and XB are logic 0. When at least either of the input signal XA or the input signal XB is logic 1, logic 1 is transmitted.
FIG. 5A
shows a dual-input exclusive OR (EXOR) gate. The foregoing logical gate is composed of 10 devices consisting of five nMOS transistors M
1
, M
3
, M
5
, M
7
and M
9
and five pMOS transistors M
2
, M
4
, M
6
, M
8
and M
10
. The drain of the nMOS transistor M
1
is connected to node N
1
, the gate of the same is connected to input signal XA, the source and the substrate respectively are connected to ground terminal Vss. The drain of the pMOS transistor M
2
is connected to node N
1
, the gate of the same is connected to the input signal XA, the source and the substrate respectively are connected to power supply terminal Vcc. Thus, a CMOS inverter is formed which is composed of the input signal XA and the output terminal N
1
. Similarly, the nMOS transistor M
3
and the pMOS transistor M
4
form a CMOS inverter having the input terminal N
1
and the output terminal N
2
. The nMOS transistor M
5
and the pMOS transistor M
6
form a CMOS inverter having the input signal XB and the output terminal N
3
.
The nMOS transistor M
7
and the pMOS transistor M
8
are CMOS transmission gates having drains commonly connected to the node N
1
and sources commonly connected to the output terminal Y. Specifically, the gate of the nMOS transistor M
7
is connected to the input signal XB and the substrate of the same is connected to the ground terminal Vss. The gate of the pMOS transistor M
8
is connected to the node N
3
and the substrate of the same is connected to the power supply terminal Vcc. The nMOS transistor M
9
and the pMOS transistor M
10
are CMOS transmission gates

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