Static information storage and retrieval – Read/write circuit – Plural use of terminal
Patent
1991-03-05
1993-01-05
Lee, John D.
Static information storage and retrieval
Read/write circuit
Plural use of terminal
36518905, 307475, G11C 1140
Patent
active
051775735
ABSTRACT:
A semiconductor memory device changeable in word organization has a plurality of input/output terminals and a plurality of input terminals. Each of the plurality of input/output terminals and the plurality of input terminals are connected to an internal circuit via input/output buffers. These input/output buffers have identical structures and arrangements with identical input/output capacitance. The output buffer in the input/output buffer connected to an input terminal is coupled to a predetermined potential. The output buffer in the input/output buffer connected to an input/output terminal is activated by an output driver. The semiconductor memory device is generally set to a 1M word.times.1 bit organization. This semiconductor memory device may be set to a 256 k word.times.4 bit organization at the time of testing.
REFERENCES:
patent: 4907203 (1990-06-01), Wada et al.
patent: 5056005 (1991-10-01), Kaneko et al.
Kohno et al, "A 14-ns 1-Mbit CMOS SRAM with Variable Bit", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, (Oct. 1988), pp. 1060-1066.
Wade et al, "A 14-ns 1 Mb CMOS SRAM with Variable Bit Organization", ISSCC Digest of Technical Papers, (Feb. 1988), pp. 252-253 and 393.
Anami Kenji
Ukita Motomu
Wada Tomohisa
Lee John D.
Mitsubishi Denki & Kabushiki Kaisha
Wise Robert E.
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