Semiconductor integrated circuit capable of testing with...

Details Semiconductor integrated circuit capable of testing with... Semiconductor integrated circuit capable of testing with...

2003-08-04

2008-11-25

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07457996

ABSTRACT:
In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.

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Notice of Grounds of Rejection in JP 2003-073951 dated Jul. 8, 2008, and Translation thereof.

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