Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-11-06
2001-06-12
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S225700, C365S230030, C365S233100, C365S189020, C365S051000, C714S710000, C714S718000
Reexamination Certificate
active
06246618
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit comprising many memories, a memory repair method for a semiconductor integrated circuit, and a computer product. In particular, this invention relates to the semiconductor integrated circuit for improving yield, a memory repair method for the semiconductor integrated circuit, and a computer product.
BACKGROUND OF THE INVENTION
In recent years, semiconductor integrated circuits have been made highly integrated and large-scale. Furthermore, the semiconductor integrated circuit now comprises a large number of memories.
FIG. 18
shows the constitution of a conventional semiconductor integrated circuit. This conventional semiconductor integrated circuit (LSI)
200
comprises many memories
201
such as RAMs and a test logic and design block
202
. The test logic is a circuit which executes a test to detect defective memories among the RAMs
201
. The design block is a circuit which uses the RAMs
201
to achieve the functions of the LSI
200
.
However, if a memory mounted on the conventional LSI becomes defective, it can not be repaired. That is, if even one memory becomes defective, the entire semiconductor integrated circuit is discarded. Consequently, the yield is poor. In particular, the greater the number of memories mounted in the semiconductor integrated circuit, the greater the probability that one of the memories of the semiconductor integrated circuit will be defective, making the yield even worse.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor integrated circuit in which yield can be increased and a method for repairing memories in the semiconductor integrated circuit.
The semiconductor integrated circuit according to one aspect of the present invention has following structure. That is, it comprises many memories; a supplementary memory; a first testing unit which performs a test to detect a defective memory among the many memories; and a supplement control unit which provides the supplementary memory in correspondence with a detected defective memory among the many memories based on a supplement control signal in accordance with the result of the test performed by the first testing unit.
According to the above invention, the first testing unit performs a test to detect a defective memory among the many memories and the supplement control unit provides the supplementary memory in correspondence with a detected defective memory among the many memories based on a supplement control signal in accordance with the result of the test performed by the first testing unit. As a consequence, the entire semiconductor integrated circuit can function regularly even when one of the memories is defective.
Further, the memories are set in a shift order, the supplementary memory being set in a last stage of the shift order. The supplement control unit carries out a shift from a subsequent stage of the detected defective memory up to the supplementary memory, thereby supplementing the detected defective memory.
According to the above invention, the supplement control unit carries out a shift from a subsequent stage of the detected defective memory up to the supplementary memory, thereby supplementing the detected defective memory. Therefore, skews between the memories can be reduced.
Further, the memories are provided continuously and in correspondence with the shift order of the supplement control unit.
According to the above invention, the memories are provided continuously and in correspondence with the shift order of the supplement control unit. Therefore, skews between the memories can be reduced.
Further, the first testing unit comprises a self-test control unit which controls the memories so that they perform simultaneously self-tests.
According to the above invention, the self-test control unit controls the memories so that they perform simultaneously self-tests. Therefore, the semiconductor integrated circuit can simultaneously test the memories by itself.
Further, a second testing unit which performs a test to detect defective detection in the first testing unit is provided.
According to the above invention, the second testing unit performs a test to detect defective detection in the first testing unit. Therefore, the reliability of the test performed by the first testing unit can be increased.
Further, a multiplying unit which multiplies a clock signal for test of the first testing unit to a predetermined frequency is provided. The first testing unit tests the actual operation and/or the speed operation margin by using the clock signal which has been multiplied by the multiplying unit.
According to the above invention, the multiplying unit multiplies a clock signal for test of the first testing unit to a predetermined frequency, and the first testing unit tests the actual operation and/or the speed operation margin by using the clock signal which has been multiplied by the multiplying unit. Therefore, a more detailed test can be carried out.
Further, a supplement control signal creating unit which automatically creates a supplement control signal based on a test result of the first testing unit is provided.
According to the above invention, the supplement control signal creating unit automatically creates a supplement control signal based on a test result of the first testing unit. Therefore, the supplement control signal can be automatically created in the semiconductor integrated circuit.
Further, the memories are different types and the first testing unit is provided commonly for the different types of memories.
According to the above invention, the first testing unit is provided commonly for different types of memories. Therefore, an increase in the circuit area can be prevented.
Further, the supplement control unit is distributed across the memories.
According to the above invention, the supplement control unit is distributed across the memories. Therefore, skews between the memories can be reduced. Furthermore, the constitution can easily be designed so as to increase memory accessing speed, and reduce the delay of signals for actual operation so as to give them priority over signals for test.
Further, a memory using circuit which uses the memories is provided, and the supplementary memory is provided on a side close to the memory using circuit.
According to the above invention, the supplementary memory is provided on a side close to the memory using circuit. Therefore, the timing deviates in an optimal direction when a memory is replaced.
Further, the memories are separately arranged in many groups and the supplementary memory is provided for each group.
According to the above invention, a supplementary memory is provided for each of the many memory groups. Therefore, memories in each group can be repaired even when the memories are separately arranged in many groups.
Further, the memories are separately arranged in many groups, and the supplementary memory is provided commonly for all or some of the memory groups.
According to the above invention, the supplementary memory is provided commonly for the memory groups. Therefore, it is possible to prevent the circuit area from increasing.
The memory repair method of a semiconductor integrated circuit comprising many memories and a supplementary memory according to another aspect of the present invention comprises following steps. That is, the step of performing a first test to detect a defective memory among the many memories; and the step of supplementing the supplementary memory in correspondence with the detected defective memory among the memories based on a supplement control signal which is in accordance with a result of the test performed in the first testing step.
According to the above invention, a first testing step performs a test to detect defects among memories, and the supplement control step provides a supplementary memory in correspondence with the detected defective memory among the memories based on a supplement control signal which is in accordance with the result of the test
Goto Koji
Okamoto Yasushi
Yamamoto Seiji
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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