Semiconductor integrated circuit capable of rapidly...

Details Semiconductor integrated circuit capable of rapidly... Semiconductor integrated circuit capable of rapidly...

2000-02-08

2001-02-27

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189090

Reexamination Certificate

active

06195298

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a circuit which generates internal power supply voltage supplied to sense amplifier.
2. Description of the Background Art
Conventionally, a semiconductor memory device has been operated by an internal power supply voltage which is generated by an incorporated internal voltage-down converter and is lower than the externally supplied power supply voltage in order to maintain its compatibility with conventional devices and also reduce power consumption.
FIGS. 26 and 27
are circuit diagrams showing configurations of conventional voltage-down converters shown in FIG.
69
and the like of Japanese Patent Laying-Open No. 3-214669. The voltage-down converter shown in
FIG. 26
generates a power supply voltage for array Vccs and includes a node NVccs for the power supply voltage for array, a differential amplifier configured of transistors
1
,
2
,
5
,
6
and
7
, a differential amplifier configured of transistors
9
,
10
,
12
,
13
and
14
, a transistor
3
, driver transistors
4
and
11
, and a capacitor
8
.
In this voltage-down converter, the differential amplifier configured of transistors
1
,
2
,
5
,
6
and
7
compares power supply voltage for array Vccs with a reference voltage Vref (e.g. 2.0V). When power supply voltage for array Vccs is lower than reference voltage Vref, transistors
4
is turned on to connect node NVccs for the power supply voltage for array to an external power supply voltage (e.g. 3.3V) node NVcc and thus raise power supply voltage for array Vccs to reference voltage Vref. Thus, power supply voltage for array Vccs is maintained at the level of reference voltage Vref.
The differential amplifier configured of transistors
9
,
10
,
12
,
13
, and
14
operates in a similar manner to the differential amplifier described above, although transistors
9
,
10
,
12
,
13
and
14
are smaller in size than transistors
1
,
2
,
5
,
6
and
7
and thus provide less power consumption.
Thus, when the semiconductor memory device is in a stand-by state, an activation signal Vdce is controlled to attain a low (L) level and the differential amplifier configured of transistors
9
,
10
,
12
,
13
and
14
only operates to reduce the power consumption of the semiconductor memory device in the stand-by state.
The voltage-down converter shown in
FIG. 27
generates a voltage VBL the magnitude of which is half that of power supply voltage for array Vccs, and includes transistors
38
-
43
.
FIG. 28
is a circuit diagram showing the configuration of a memory cell array portion of a conventional semiconductor memory device. As shown in
FIG. 28
, the memory cell array portion includes bit lines BL
0
and BLn, inverted bit lines /BL
0
and /BLn, a p-type sense amplifier configured of transistors
16
-
19
, a transistor
15
supplying a power supply voltage for array Vccs to the p-type sense amplifier, an n-type sense amplifier configured of transistors
20
-
23
, a transistor NT
1
supplying a ground voltage to the n-type sense amplifier, a bit line equalization circuit configured of transistors
24
-
29
, word lines WL
0
and WLm, memory cells MC
0
to MC
3
, and parasitic capacitances CB
0
to CB
2
n+1. Memory cell MC
0
includes a capacitor
34
and a transistor
30
, memory cell MC
1
includes a capacitor
35
and a transistor
31
, memory cell MC
2
includes a capacitor
36
and a transistor
32
, and memory cell MC
3
includes a capacitor
37
and a transistor
33
.
Data of high (H) or L held in memory cells MC
0
to MC
3
correspond to power supply voltage for array Vccs or 0V applied to capacitors
34
,
35
,
36
and
37
. The pairs of bit lines are precharged to attain an intermediate voltage (½ Vccs, i.e., voltage VBL) in reading the data held in memory cells MC
0
to MC
3
. Then, when word line WL
0
is selected, for example, to connect capacitors
34
and
35
in memory cells MC
0
and MC
1
to bit lines BL
0
and BLn. If capacitors
34
and
35
hold data of H, the voltage of bit lines BL
0
and BLn exceeds voltage VBL. If capacitors
34
and
35
hold data of L, the voltage of bit lines BL
0
and BLn drop below voltage VBL. Meanwhile, the voltages of inverted bit lines /BL
0
and /BLn remain at voltage VBL and potential differences are caused between paired bit lines. The potential differences are amplified by the sense amplifiers to determine the data held in memory cells MC
0
and MC
1
.
A data read operation when memory cells MC
0
and MC
1
hold data of H will now be described with reference to the timing charts shown in
FIGS. 29A-29G
. The state prior to time t1 is a stand-by state, and a bit line equalization signal BLEQ is at a high level, as shown in
FIG. 29F
, and paired bit lines BL
0
and IBL
0
, and BLn and /BLn are precharged via transistors
24
-
29
to attain voltage VBL. When word line WL
0
is activated to attain a high level at time t2, as shown in
FIG. 29C
, transistors
30
and
31
are turned on to allow the data of H to be transmitted on bit lines BL
0
and BLn and the voltage of bit lines BL
0
and BLn exceeds voltage VBL, as shown in FIG.
29
B. Meanwhile, the voltage of inverted bit lines /BL
0
and /BLn remains at voltage VBL and a potential difference is thus created between paired bit lines BL
0
, /BL
0
, BLn and /BLn. At time t3, sense amplifier activation signals SEP and SEN respectively attain a low level and a high level, as shown in
FIGS. 29D and 29E
, to turn on transistors
15
and NT
1
and activate both the p-type sense amplifier configured of transistors
16
-
19
and the n-type sense amplifier configured of transistors
20
-
23
. Thus, at time t4, the voltages of bit lines BL
0
and BLn are raised to power supply voltage for array Vccs and the voltages of inverted bit lines /BL
0
and /BLn are lowered from voltage VBL to the ground voltage. When the voltages of bit lines BL
0
and BLn recover to the power supply voltage Vccs for array in the stand-by state, i.e. 2.0V, at time t5, the power supply voltage Vccs for array in the stand-by state, i.e. 2.0V, is rewritten into capacitors
34
and
35
as a holding voltage for capacitors
34
and
35
which have been lowered in reading the data.
For conventional semiconductor memory devices, however, the power supply voltage for array Vccs when the sense amplifiers operate drops from a predetermined level (2.0V) when the voltages of bit lines BL
0
and /BLn are raised from voltage VBL at time t4, as shown in FIG.
29
A. Then the voltage-down converter shown in
FIG. 26
operates and the dropped power supply voltage for array Vccs thus recovers to the predetermined level, although the recovery requires a certain period of time. In other words, bit lines BL
0
and BLn each attain a high level by supply of power supply voltage for array Vccs and accordingly the time for amplifying a potential difference of a pair of bit lines depends on the operating time of the voltage-down converter shown in FIG.
26
. Thus, it has been difficult for conventional semiconductor memory devices to rapidly rewrite data into memory cells.
By contrast, Japanese Patent Laying-Open No.
6
-
215571
discloses the semiconductor memory device shown in FIG.
30
. As shown in
FIG. 30
, the semiconductor memory device includes a pair of bit lines BL and /BL, word lines WL
1
and WL
2
, a precharger circuit PC, input/output data lines I/O and /I/O, a sense amplifier, a node NVccs for power supply voltage for array, transistors Q
2
and Q
15
, a voltage-down converter BVDL connected to node NVccs for power supply voltage for array, and a parasitic capacitance C
1
connected to node NVccs for power supply voltage for array, wherein voltage-down converter BVDL includes transistors Q
51
-Q
56
.
An operation of the semiconductor memory device will now be described.
Parasitic capacitance C
1
is charged to attain an external power supply voltage Vcc when transistor Q
2
is turned on while transistor Q
15
is turned off and the sense amplifier

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