Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-06-21
2004-05-25
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S017000, C326S035000, C326S036000
Reexamination Certificate
active
06741100
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-137269, filed May 13, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-speed circuit operation of a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1
is a graph showing a relationship between the size ratio of an n-channel MOS transistor to a p-channel MOS transistor (Wn/Wp) and each of rise delay time and fall delay time in a semiconductor integrated circuit. As is seen from this graph, the larger the size of the n-channel MOS transistor, the shorter the fall delay time, whereas the smaller the size of the p-channel MOS transistor, the longer the rise delay time.
In the design of prior art semiconductor integrated circuits, two transitions from a low-level voltage to a high-level voltage and from a high-level voltage to a low-level voltage are effected. The Semiconductor integrated circuits are usually so designed that rise delay time and fall delay time become equal to each other. The reason is as follows. If these two times differ from each other, a signal is delayed in transmission due to a slower transition and thus an operating frequency cannot be increased.
In a domino circuit, only one of rise and fall transitions is considered to be significant. The domino circuit can thus be designed so as to increase the speed of only one transition.
In the domino circuit, however, once a signal makes a transition, it cannot be restored. Therefore, only the positive logic that limits the transition to one direction can be treated, thus increasing the number of logic stages in the circuit. Since the domino circuit is susceptible to noise, it is difficult to design automatically.
BRIEF SUMMARY OF THE INVENTION
A semiconductor integrated circuit according to an aspect of the present invention comprises a standard cell in which rise time when an output transitions from a low-level voltage to a high-level voltage and fall time when an output transitions from the high-level voltage to the low-level voltage differ from each other and a flip-flop which outputs a first input signal, which is input in a cycle immediately before a clock signal in synchronization with one of rise and fall of the clock signal, to the standard cell and then fixes an output at one of a high-level voltage and a low-level voltage, the flip-flop being provided in a stage precedent to the standard cell, wherein before a second input signal, which is output from the flip-flop after the first input signal, reaches the standard cell, an output of the standard cell is set at one of a high-level voltage and a low-level voltage, which corresponds to a signal whose transition speed is slow, by one of the high-level voltage and the low-level voltage that is output from the flip-flop.
A method of designing a semiconductor integrated circuit according to another aspect of the present invention, comprises expressing a logic circuit having standard cells by a logical polynomial, searching the logical polynomial for complementary signals, duplicating a logical polynomial to generate the complementary signals when the complementary signals are detected, forming a logic circuit in accordance with the duplicated logical polynomial, and increasing one of a rise transition and a fall transition in speed in each of the standard cells.
REFERENCES:
patent: 5495188 (1996-02-01), Chen et al.
patent: 5517136 (1996-05-01), Harris et al.
patent: 6154045 (2000-11-01), Ye et al.
patent: 2002/0008545 (2002-01-01), Zama et al.
Itaka Yasuhito
Kamei Takayuki
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