Semiconductor integrated circuit capable of adjusting the...

Details Semiconductor integrated circuit capable of adjusting the... Semiconductor integrated circuit capable of adjusting the...

2005-12-06

2005-12-06

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S230080, C365S230020, C365S189050

Reexamination Certificate

active

06973001

ABSTRACT:
The gates of each pair of second transistors receive a pair of delayed timing signals whose rising and falling edges are adjacent to each other, respectively, and gradually discharge the charges at a first node pre-charged to a first power supply voltage. The discharge speed varies depending on the threshold voltage, operating temperature, and power supply voltage of the transistors. A plurality of detection circuits operates at timings different from each other to detect the voltage at the first node as logic values. A selector selects any one of the second timing signals depending on a detection result provided by the detection circuit. An internal circuit operates in synchronization with the second timing signal selected. Accordingly, the operation timing of the internal circuit can be optimally adjusted in response to a change in operating environments. This allows the improvement in operation margin of the semiconductor integrated circuit.

REFERENCES:
patent: 5708684 (1998-01-01), Ueda
patent: 6757212 (2004-06-01), Hamamoto et al.
patent: 2002/0141280 (2002-10-01), Haramoto et al.
patent: 09-116342 (1997-05-01), None
patent: 2003-163584 (2003-06-01), None

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