Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1993-05-25
1995-03-07
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 21, 326101, 327292, H03K 19096
Patent
active
053961293
ABSTRACT:
In a semiconductor integrated circuit apparatus, a first logic circuit processes a clock signal inputted through an external clock input terminal, and each of a plurality of second logic circuits processes the clock signal outputted from the first logic circuit, and outputs the processed clock signal to a plurality of flip-flops. In the semiconductor integrated circuit apparatus, an inner clock signal line is provided for electrically connecting the plurality of second logic circuits with the plurality of flip-flops, wherein the inner clock signal line is formed in a ring shape in the periphery of the semiconductor integrated circuit apparatus so that the plurality of flip-flops are located within the inner clock signal line, thereby reducing the clock skews therebetween in the semiconductor integrated circuit. Furthermore, an outer clock signal line is provided for electrically connecting the first logic circuit with the plurality of second logic circuits, and then the outer clock signal line is formed in a ring shape, thereby further reducing the clock skews therebetween in the semiconductor integrated circuit.
REFERENCES:
patent: 4661721 (1987-04-01), Ushika
patent: 4851717 (1989-07-01), Yabe
patent: 5013942 (1991-05-01), Nishimura et al.
patent: 5029279 (1991-07-01), Sasaki et al.
patent: 5109168 (1992-04-01), Rusu
Hudspeth David R.
Matsushita Electronics Corporation
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