Semiconductor integrated circuit apparatus and method of adjusti

Details Semiconductor integrated circuit apparatus and method of adjusti Semiconductor integrated circuit apparatus and method of adjusti

1996-02-06

1997-07-29

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Data refresh

365149, G11C 1300

Patent

active

056527292

ABSTRACT:
A semiconductor Integrated circuit apparatus that has memory cell array, and a refresh timer which outputs a refresh signal for holding data of the memory cell array. The apparatus also has a leak monitoring circuit for detecting a voltage drop associated with a leak current from the memory cell array of a main memory, and a pulse generating circuit for outputting the refresh signal. The leak monitoring circuit is formed by a dummy memory cell array, which is formed by memory cells having the same structure as the memory cells of the main memory, a potential comparator for comparing a potential which is outputted from the dummy memory cell array with a predetermined potential, and leak accelerating means for accelerating the potential decrease speed of the dummy memory cell array.

REFERENCES:
patent: 4905198 (1990-02-01), Oishi
patent: 4939695 (1990-07-01), Isobe
patent: 5392251 (1995-02-01), Manning

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