Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-06-25
2003-07-08
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S028000, C326S095000, C326S096000, C326S119000, C326S121000
Reexamination Certificate
active
06590425
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus which forms elements such as a central processing unit, peripheral units and memory units which are components of a computer and, more particularly, a semiconductor integrated circuit apparatus such as, for example, a semiconductor integrated circuit apparatus for use in a parallel computer and aerospace applications which are required to provide high reliability and performance.
2. Description of the Related Art
Lately, computers have been remarkably advanced in their performance. A representative circuit technology which has supported such progress of computer performance is found in completely complementary static CMOS (complementary metal oxide semiconductor) circuits. The completely complementary static CMOS circuit requires less power consumption and excels in high efficiency of integration, as compared with a bipolar transistor circuit. As is well known, such CMOS circuits are comprised of a P-type logic block composed of P-type MOS transistors and an N-type logic block composed of N-type MOS transistors which are connected in series, wherein the two logic blocks operate complementarily. A rise time of an output signal depends on the characteristics of the PMOS transistors and a fall time of the output signal depends on the characteristics of the NMOS transistors. Generally, a gain factor &bgr; of the PMOS transistors is smaller than the gain factor &bgr; of the NMOS transistors. Accordingly, if channel widths and channel lengths of the PMOS transistors and NMOS transistors are designed to be equal, the rise time of the output signal is longer than the fall time. On the contrary, the channel widths of PMOS transistors need to be larger than the channel widths of NMOS transistors to make the rise time and the fall time of the output signal equal, resulting in an increase of input capacitance and area.
A CMOS domino logic circuit is one example of a circuit for solving a problem of the above-described completely complementary static CMOS circuit (R. H. Krambeck, Charles M. Lee and Hung-Fai Stephen Law, “High-speed Compact Circuits with CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 3, 1982). An example of such a CMOS domino circuit is shown in FIG.
9
. The CMOS domino circuit is a dynamic circuit which forms a logic circuit using only NMOS transistors. Accordingly, a delay in signal propagation depends on the characteristics of the NMOS transistors. In the CMOS domino circuit, there is no problem of an increase of the delay time resulting from the P-type logic block which is the problem in the completely complementary static CMOS circuit. Since the logic is formed only with the NMOS logic block and the input capacitance and the parasitic capacitance in the circuit, the operation is carried out at a high speed and the area is small.
However, the CMOS domino circuit includes the following three problems. The first problem is that, since the CMOS domino circuit is a dynamic circuit, it is very susceptible to &agr; particle noise. A circuit diagram and operating waveform for such a circuit are shown in FIG.
10
. The CMOS domino circuit precharges a clock signal to be entered into the circuit during a period when the clock signal remains at a low level, and the logic is propagated during the period when the clock signal remains at a high level. When an input signal is at a low level while the clock signal remains at a high level for a logic decision, a node point A remains at a high level and the charge at the point A is dynamically maintained. At this time, if &agr; particles hit the drain of the N-type transistor
100
, the charge at the point A is discharged and the potential level at the point A lowers. There is no path for charging the discharged electric charge. Therefore the potential level, which has been lowered, does not return to the previous level, and a faulty operation results.
The second problem is that the CMOS domino circuit, which is a dynamic circuit, is susceptible to leakage current noise. When an input signal is at a low level while the clock signal remains at a high level for determination of the logic, a node point A remains at a high level and the charge at the point A is dynamically maintained. At this time, the charge at the point A is discharged by the leakage current through the N-type transistor and the potential level at the point A lowers. There is no path for charging the discharged electric charge and therefore the potential level, which has been lowered, does not return to the previous level and a faulty operation results.
The third problem is a problem related to a charge redistribution effect as shown in
FIG. 11. A
capacitance of the node point A of the CMOS domino circuit is assumed as CA and a capacitance of the node point B is assumed as CB. If the input signal A is at the low level and the input signal B is at the high level in the logic decision period
1
, the potential of the node point A remains at the high level “Vdd” and the potential of the node point B remains at the low level “0V”. Since NMOS transistors
101
and
102
are kept off during the precharging period, the potential at the node point A remains at the high level “Vdd” and the potential at the node point B remains at “0V”. When the input signal A is set to the high level in the logic decision period
2
, the NMOS transistor A turns to ON, the charge is redistributed between the node point A and the node point B and the potential of the node points A and B is “(CA/(CA+CB)) Vdd”. When the capacitances of CA and CB are substantially equal, the potential of the node points A and B is “(½) Vdd” which leads to a faulty operation.
As a means for solving the problems of the CMOS domino circuit such an, for example, &agr; particle noise, leakage current and charge redistribution effect, there has been proposed a method for adding a feedback type pull-up PMOS transistor
103
shown in FIG.
12
. The electric charge to be discharged due to &agr; particle noise and charge redistribution effect is compensated by weakly pulling up the point A of the dynamic node with the feedback type pull-up PMOS transistor
103
. However, when the N-type logic block
104
draws out the charge at the node point A to a low level, the feedback type pull-up PMOS transistor
103
prevents this drawing-out operation. The through current flows to cause not only the power consumption to increase but also the switching speed of the circuit to remarkably lower. Accordingly, this means impaired high speed operation and is therefore unsuitable for a system which requires high speed operation of the circuit.
A static circuit for speeding up the completely complementary static CMOS circuit by precharging in advance of the output is disclosed in Japanese Patent Application Disclosure Gazette HEI. 2-277315. However, this circuit comprises circuits for precharging the output to a high level voltage and circuits for precharging the output to a low level voltage which are alternately series-connected and operated and therefore PMOS transistors and NMOS transistors alternately operate and the signals cannot be propagated only through NMOS transistors.
As described above, though the CMOS domino circuit is proposed as a circuit which operates at a higher speed than the completely complementary static CMOS circuit, the CMOS domino circuit includes a problem that it is susceptible to noise. On the contrary, if the feedback type pull-up PMOS transistor is added to make the circuit less susceptible to noise, the high speed operation of the circuit is impaired. To solve these problems, the present invention is intended to provide compatibility of high noise tolerance and high speed operation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a circuit which is not susceptible to noise and which operates at a higher speed than the conventional completely complementary static CMOS circuit.
A semiconductor integrated circuit apparatus accordin
Hotta Takashi
Murabayashi Fumio
Yamada Hiromichi
Yamauchi Tatsumi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Michael G.
Paik Steven S.
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