Semiconductor integrated circuit and the same checking method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment

Reexamination Certificate

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Details

C714S711000, C714S718000, C714S723000, C714S736000, C714S799000, C714S807000, C714S808000, C714S005110, C714S006130, C714S006130, C714S042000, C324S763010, C365S201000

Reexamination Certificate

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07657798

ABSTRACT:
A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.

REFERENCES:
patent: 2002/0062458 (2002-05-01), Maeno
patent: 2002/0125907 (2002-09-01), Kurtulik et al.
patent: 2005/0076274 (2005-04-01), Nagai et al.
patent: 64-23465 (1989-01-01), None
patent: 7-272411 (1995-10-01), None

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