Semiconductor integrated circuit and testing method therefor

Details Semiconductor integrated circuit and testing method therefor Semiconductor integrated circuit and testing method therefor

2007-02-13

2008-08-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000

Reexamination Certificate

active

07414905

ABSTRACT:
The present invention provides a semiconductor integrated circuit that is provided with an address generation circuit that selectively generates an address of a memory cell substituted by a redundancy memory cell based on a defective memory cell address retained in an address retention circuit, and a control circuit that selectively tests the redundancy memory cell by performing a retest on whether the substitution is successful or not based on the address generated by the address generation circuit.

REFERENCES:
patent: 6067262 (2000-05-01), Irrinki et al.
patent: 6091649 (2000-07-01), Choi
patent: 6388929 (2002-05-01), Shimano et al.
patent: 6625072 (2003-09-01), Ohtani et al.
patent: 6728910 (2004-04-01), Huang

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