Semiconductor integrated circuit and semiconductor logic...

Details Semiconductor integrated circuit and semiconductor logic... Semiconductor integrated circuit and semiconductor logic...

2001-04-24

2004-01-13

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S112000, C326S119000

Reexamination Certificate

active

06677782

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit suitable for speeding up a decoder circuit of a semiconductor memory for example and reducing the power consumption and a semiconductor logic circuit used for the semiconductor integrated circuit.
In a semiconductor memory which is an example of a semiconductor integrated circuit, a decoder circuit shown in
FIG. 16
is heretofore used. As shown in
FIG. 16
, BU denotes an address buffer, PD denotes a predecoder, DD denotes a main decoder, A
10
to A
32
denote address input, XB
1
to XB
3
denote the output of a buffer (or a buffer output line), XPD
1
to XPD
3
denote the output of a predecoder (or a predecoder output line), W
1
to W
512
denote a word line,
1
denotes an inverter,
2
denotes a static NAND logic circuit,
3
denotes a dynamic NAND logic circuit and &phgr; denotes a control signal. In
FIG. 16
, a circuit configuration including 512 word lines is shown. Reference numbers
1
to
3
denote a general inverter and NAND logic circuits respectively composed by a complimentary field effect transistor (an N-type transistor and a P-type transistor) shown in FIG.
17
. It is supposed that a transistor is a metal oxide silicon field effect transistor (a MOS transistor) and it will be described below.
As shown in
FIG. 16
, the buffer output line XB
1
is switched to a high level or a lower level according to the level of electric potential of each address input A
10
to A
12
. A control signal &phgr; is input to the NAND logic circuit
3
in the predecoder PD at timing a little delayed from the buffer output XB
1
. A phase in which the control signal &phgr; is at a low level is a precharge phase and a phase in which it is at a high level is a evaluation phase. Therefore, when a control signal &phgr; is switched from a low level to a high level and enters a evaluation phase, the output of the NAND logic circuit
3
to which only one buffer output signal at a high level is input changes from a high level to a low level, one of the predecoder output lines XPD
1
is switched from a low level to a high level via the inverter and is selected.
Similarly, the buffer output line XB
2
is switched to a high level or a low level according to the level of electric potential of each address input A
20
to A
22
. The output of the NAND logic circuit
2
to which only one buffer output signal at a high level is input changes to a low level, one of the predecoder output line XPD
2
is switched to a high level via the inverter and is selected. Similarly, one of the predecoder output line XPD
3
is switched to a high level according to the level of electric potential of each address input A
30
to A
32
and is selected. The output of the NAND logic circuit
3
in the main decoder to which only one signal at a high level output from the predecoder is input changes to a low level, one of the word lines W
1
to W
512
is switched to a high level via the inverter and is selected.
In a conventional type circuit, at least two columns of inverters are required to acquire the true of address input and a complementary signal for a buffer output line. In
FIG. 16
, four columns of inverters are shown in the address buffer BU. The third and fourth columns of inverters are provided for a driver to acquire the true and a complementary signal to the buffer output line, the second column of inverter is provided for driving the inverters and the first column of inverter is provided for shaping input. In the meantime, as to the NAND logic circuits
2
and
3
shown in
FIG. 16
, the more the number of inputs is as shown in
FIG. 17
, the more the number of the columns of N-type transistors MN
1
to MNn for pulling down output is (on-state resistance is increased) and the speedup of circuit operation is prevented.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and its complementary output signal having approximately the same delay time are acquired and to speed up a decoder circuit by the above semiconductor logic circuit. The object is also to reduce the power consumption of the decoder circuit.
The speed up of the decoder circuit which is one of the above objects is achieved by using a semiconductor logic circuit controlled for precharge and evaluation operation according to the polarity of a control signal input to its control terminal and having configuration that the number of columns of transistors for pulling down at an output node is at most 2 or 3 even if the number of input signals (inputs) is many, the true and a complementary output signal having approximately the same delay time are acquired and the electric potential of either of the above outputs is used for reference electric potential for the above input signals for at least either circuit configuring the decoder circuit. The reduction of the power consumption of the decoder circuit is achieved by controlling the control terminal of the semiconductor logic circuit used for a predecoder or a main decoder by a signal output from the preceding circuit.


REFERENCES:
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5373203 (1994-12-01), Nicholes et al.
patent: 5640108 (1997-06-01), Miller
patent: 10150358 (1998-06-01), None

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