Semiconductor integrated circuit and semiconductor...

Details Semiconductor integrated circuit and semiconductor... Semiconductor integrated circuit and semiconductor...

2001-02-16

2003-02-04

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S102000

Reexamination Certificate

active

06515511

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention broadly relates to a semiconductor integrated circuit and a semiconductor integrated circuit device.
Generally, an FPGA (Field Programmable Gate Array) has been well-known as a logic semiconductor integrated circuit having a plurality of transfer gates.
Herein, it is to be noted that the FPGA means a gate array type semiconductor integrated circuit in which a user can freely change logic.
Meanwhile, disclosure has been made about the conventional general structure of the FPGA in Japanese Unexamined Patent Publication No. Hei. 9-148440, as illustrated in FIG.
1
.
In such a conventional example, variable logic blocks PLB and switch matrixes SMX are alternatively arranged in vertical and lateral directions at a central portion of a chip SUB.
With this structure, the variable logic block PLB can change a logic function while the switch matrix SMX can change a connection state between wiring patterns.
Further, a X-decoder circuit X-DEC and a Y-decoder and writing circuit Y-DEC & WDR, which selects memory cells placed in the variable logic block PLB and the switch matrix SMX to write data signals, are arranged around the variable logic blocks PLB and the switch matrixes SMX.
Moreover, input-output buffer cells IOB are arranged along the periphery of the chip so as to surround these circuits.
The variable logic block PLB includes the transfer gates for changing the logic, memory cells, and inverters for controlling signals given to the transfer gates.
On the other hand, the switch matrix SMX comprises the transfer gates and the memory cells for controlling ON/OFF operations of the transfer gates. Herein, the transfer gate is composed of an n-channel MOS transistor.
Each of the variable logic block PLB and the switch matrix SMX is occupied by the transfer gates with approximately ⅙ of the total number of the transistors.
Referring to
FIG. 2
, a p-type well
102
is formed on a silicon substrate
101
in a SMX formation region while a p-well
103
is formed in a PLB formation region.
In this event, a MOSFET Qn
1
having a gate electrode G
1
and source/drain regions
105
is formed in the SMX formation region while a MOSFET Qn
2
having a gate electrode G
2
and source/drain regions
106
is formed in the PLB formation region.
Further, interlayer insulating films
111
to
115
are deposited on the silicon substrate
101
. Moreover, a first layer metal wiring pattern M
1
, a second metal layer wiring pattern M
2
, a third layer metal wiring pattern M
3
, and a fourth layer metal wiring pattern M
4
are placed between the interlayer insulating films.
An output signal of the PLB formation region is produced from the drain region of the MOSFET Qn
2
, and is transmitted to the SMX formation region via the metal wiring patterns M
1
, M
2
, and M
3
.
Further, the signal is sent to the fourth layer metal wiring pattern M
4
through the MOSFT Qn
1
serving as a switching transistor, and is transmitted to another switch matrix SMX (not shown) via another variable logic block PLB. Herein, the ON/OFF operation of the MOSFET Qn
1
is controlled by a memory device, such as, an SRAM.
In such a programmable logic integrated circuit, a plurality of transfer gates are connected to the wiring pattern. However, the transfer gate is structured by the MOS transistor formed on the silicon substrate in the conventional example.
In consequence, the junction capacitance of the transistor parasites to the wiring pattern, and thereby, the wiring pattern inevitably has large parasitic capacitance.
Further, every when the transfer gate is inserted into the wiring pattern, the wiring pattern is pulled down from the third layer and the fourth layer into the substrate surface. Thereafter, the wiring pattern is pulled up to an upper layer.
Consequently, a wiring length becomes long, and parasitic capacitance is more increased with an increase of parasitic resistance.
Further, all transistors including the transfer gates are formed on the same plane in the conventional example. As a result, each of the switch matrix SMX and the variable logic block PLB has a large area.
To this end, the number of the gates, which can arrange for one chip of the FPGA, is reduced so as to restrict an applied system.
Such a problem is not inherent to the FPGA, and is common to various programmable devices which includes a plurality of switches consisting of the transfer gates other than the FPGA.
Moreover, a chip having a learning function, such as, a digital neuron chip LSI, also includes a plurality of transfer gates, and has the above-mentioned problem.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an integrated circuit and device which are capable of reducing parasitic capacitance and parasitic resistance for a wiring pattern of an integrated circuit, such as, a FPGA, and of achieving a high speed operation of an integrated circuit having a plurality of transfer gates.
It is another object of this invention to provide an integrated circuit and device which are capable of realizing high density and high integration of an integrated circuit, and of increasing the number of transfer gates.
According to this invention, a semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate.
With this structure, each of the basic cells includes a wire selection portion and a logic gate portion.
Further, the logic gate portion has a MOS transistor.
Moreover, the wire selection portion has a thin-film transistor (TFT) serving as a transfer gate.
In this condition, the wire selection portion is placed over the logic gate portion via an interlayer insulating film.
In this event, the thin-film transistor may be an n-channel enhancement type or an n-channel depletion type thin-film transistor.
Further, a pair of wiring patterns are formed in the interlayer insulating film, and the thin-film transistor is placed between the wiring patterns.
The thin-film transistor preferably comprises any one of a lateral type and a vertical type.
The thin-film transistor may have at least a channel region, and the channel region may be formed by a non-doped polysilicon film.
More specifically, the transfer gate, which can change the connection path between the wiring patterns, is formed on the semiconductor substrate via the insulating film. The junction capacitance of the TFT formed on the insulating film is excessively small in comparison with the bulk-type transistor.
Further, it is possible to arrange the transfer gate between the wiring patterns. Thereby, it is prevented the wiring pattern from being lengthened by inserting the transfer gate into the wiring pattern. Consequently, the parasitic capacitance of the wiring pattern can be more reduced, and further, the parasitic resistance can be lowered also.
Accordingly, the high speed of the circuit operation can be realized by the structuring the transfer gate with the TFT in the logic integrated circuit, such as, the FPGA, in which the transfer gate for switching a plurality of wiring patterns is connected to the wiring pattern.
Further, the transfer gate, which is can change the connection path between the wiring pattern, is formed on the semiconductor substrate via the insulating film, as mentioned above. Consequently, the number of the devices arranged on the semiconductor substrate as the bulk device is reduced, and thereby, the chip area can be reduced also. If the chip areas are identical to each other, the gate number can be increased with the increase of the device number.
Meanwhile, it has been well known that the three-dimensional integrated circuit provides the high integration. However, a part of device has been not conventionally structured by the TFT in the logic integrated circuit, such as, the FPGA. This is because the TFT has a delay operation, a large leak, and a low heat-dissipating characteristic.
Therefore, it has been considered that the logic integrated circuit having high function and high performance can no

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