Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2011-03-15
2011-03-15
Beausoliel, Robert (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S710000, C365S201000
Reexamination Certificate
active
07908527
ABSTRACT:
A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.
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Japanese Office Action for JP2007-206952 mailed on Aug. 25, 2009.
Japanese Office Action for 2007-206952 Mailed Aug. 31, 2010.
Hojo Takehiko
Kohara Koji
Beausoliel Robert
Kabushiki Kaisha Toshiba
Nguyen Steve
Turocy & Watson LLP
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