Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-02-07
2003-11-25
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S098000
Reexamination Certificate
active
06653865
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which an internal circuit operates with a pulse signal.
For example, in a memory macro, the internal circuit operates with a pulse signal. Therefore, it is required to generate a pulse signal that is supplied to the internal circuit on the basis of the clock that is externally supplied.
FIG. 1
illustrates a prior art circuit for generating a pulse signal to be used within the memory macro.
The circuit illustrated in
FIG. 1
is formed of a signal input circuit
1
, a signal latch circuit
2
and a pulse signal generating circuit
3
.
In the signal input circuit
1
, an address signal A is supplied from an address signal input terminal
4
. The address signal A is supplied to a signal latch circuit
2
as an inverted address signal/A (hereinafter/A is identical to A-bar, indicating the inverted value of A) via an inverter
9
. Moreover, the address signal A is supplied to the signal latch circuit
2
via the inverter
9
and inverter
10
.
In the signal latch circuit
2
, the address signal A or a clock signal LCK is supplied to the clock signal terminal
5
for latching. The inverted address signal/A is supplied to a transmission transistor
12
and the address signal A is supplied to a transmission transistor
13
.
The clock signal LCK for latching and the inverted clock signal/LCK for latching, which is inverted by the inverter
11
, are supplied to the transmission transistor
12
and transmission transistor
13
, respectively. Any one of the transmission transistor
12
or transmission transistor
13
becomes conductive in the predetermined timing on the basis of the clock signal LCK for latching and any one of the address signal A or inverted address signal/A is latched (stored and held) in the latch circuit (memory circuit) formed of the inverter
14
and inverter
15
.
The pulse signal generating circuit
3
is formed of a NAND circuit
16
and a NAND circuit
17
. The inverted address signal/A is stored and held by the NAND circuit
16
when the transmission transistor
12
becomes conductive and the clock signal ICK for the internal circuit are supplied. The address signal A is stored and held by the NAND circuit
17
when the transmission transistor
13
becomes conductive and the clock signal ICK for the internal circuit are supplied.
The pulse signal generating circuit
3
generates a pulse signal and is outputted from the output terminal
7
and output terminal
8
, and is then supplied to the internal circuit.
FIG. 2
is a timing chart showing the address signal A change to a low level (LOW LEVEL) in the circuit of
FIG. 1
when the address signal A is supplied to the address signal input terminal
4
.
(1) The address signal A changes to the low level.
(2) The clock signal LCK for latching changes to the low level.
When such signal level change, the transmission transistor
12
becomes conductive and the high-level inverted address signal/A is latched by the latch circuit.
(3) The clock signal LCK for internal circuit changes to the high level.
When such signal level change, the high level inverted address signal/A is supplied to one of the input terminals of the NAND circuit
16
and the high level clock ICK for the internal circuit is supplied to the other input terminal. While the clock signal ICK for the internal circuit is in the high level, the low-level pulse signal AO is outputted from the output terminal
7
.
In order to latch the address signal, the setup time ST
1
and hold time HT
1
to the clock signal LCK for latching is required.
Moreover, since it is required to generate a pulse signal after the address signal is reliably latched with the latch circuit, it is also required to provide the setup time ST
2
to the clock signal CLK for the internal circuit.
As explained above, two setup times ST
1
and ST
2
are required until the pulse signal supplied to the internal circuit is generated from the input of the address signal. The prior art for generating the pulse signal has a problem wherein a certain period of time is required for generating a pulse signal from the input of the address signal. Therefore, high speed operation cannot be realized.
SUMMARY OF THE INVENTION
In order to solve the problems explained above, the present invention provides a semiconductor integrated circuit comprising a signal input circuit for receiving an input signal and providing an output signal without holding the input signal or an inverted signal thereof; and a pulse signal generating circuit for generating a pulse signal to be supplied to an internal circuit based on a signal outputted from the signal input circuit and a first clock signal.
Moreover, the present invention provides a semiconductor integrated circuit in which a circuit for holding an input signal or an inverted input signal is not provided on the signal path that is sequentially connected to the signal input circuit for receiving an input signal; and it provides an output without holding the input signal or an inverted signal thereof. A pulse signal generating circuit generates a pulse signal to be supplied to an internal circuit based on the signal outputted from signal input circuit and a first clock signal.
The present invention also provides a semiconductor integrated circuit which comprises a signal input circuit for receiving an input signal and providing an output signal without holding the input signal or an inverted signal thereof. A pulse signal generating circuit generates a pulse signal to be supplied to an internal circuit based on the signal outputted from the signal input circuit, a first clock signal and a third clock signal.
The semiconductor integrated circuit of the present invention generates a pulse signal without latching (storing or holding) the input signal. Therefore, a setup time for latching (storing or holding) the input signal is not required. The time required for generating the pulse signal from the input of address signal may be shortened and high-speed circuit operation may be realized. Moreover, a pulse signal can be generated with a simplified circuit structure and the circuit structure can be reduced in size.
According to the present invention, the pulse signal may be generated without latching (storing or holding) the input signal. Therefore, the setup time for latching the input signal is no longer required and the time required for generating a pulse signal from the input of the address signal can be shortened and high-speed circuit operation can also be attained. Moreover, the pulse signal can be generated with a simplified circuit structure and the circuit configuration can be reduced in size.
REFERENCES:
patent: 5590081 (1996-12-01), Shimizu
patent: 5723993 (1998-03-01), Cha
patent: 5742192 (1998-04-01), Banik
patent: 5896341 (1999-04-01), Takahashi
patent: 6020763 (2000-02-01), Gabillard
patent: 6111444 (2000-08-01), Mikan, Jr. et al.
patent: 6124737 (2000-09-01), Lan et al.
patent: 6127850 (2000-10-01), Lan et al.
patent: 6154045 (2000-11-01), Ye et al.
patent: 6232797 (2001-05-01), Choi et al.
Akiyoshi Hideo
Shimizu Hiroshi
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
Tan Vibol
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