Semiconductor integrated circuit and operating method

Details Semiconductor integrated circuit and operating method Semiconductor integrated circuit and operating method

2001-08-27

2003-06-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189050

Reexamination Certificate

active

06577546

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor integrated circuit and operating method and more particularly a semiconductor device having a memory and logic circuit integrated in which a burn-in test may be simultaneously executed.
BACKGROUND OF THE INVENTION
As the operating speed of a microprocessor unit (MPU) increases, the system memory is also required to increase its operating speed. The system memory typically includes a dynamic random access memory (DRAM). If the operating speed of DRAM fails to increase along with the operating speed of the logic included in the MPU, the processing performance becomes limited by the operating speed of the DRAM. To solve this problem, a semiconductor integrated circuit has been developed in which a DRAM and logic are both integrally placed on the same semiconductor chip.
In a semiconductor device, a burn-in test is commonly performed after manufacturing in order to screen and eliminate initial latent defects (infant mortality). A burn-in test subjects the semiconductor device to stress by applying high temperature (e.g., 125° C.) and a power supply voltage above the rated voltage indicated by the specification in which the device is guaranteed to reliably operate.
It is desired, in semiconductor integrated circuit having DRAM and logic, to simultaneously apply stress to both the DRAM and logic circuits during the burn-in test, thus, reducing test time and decreasing costs.
Japanese Laid-Open Patent Publication No. Hei 11-134900 discloses a semiconductor integrated circuit capable of applying a burn-in test to both a memory and a logic circuit. Such a semiconductor integrated circuit is illustrated in FIG.
1
.
Referring now to
FIG. 1
, a block schematic diagram of a conventional semiconductor integrated circuit is set forth and given the general reference character
101
.
Conventional semiconductor integrated circuit
101
includes a DRAM
102
and a logic circuit
103
.
Logic circuit
103
includes multiplexers (
108
to
111
). In the burn-in operation, a signal is externally input into logic circuit
103
. Logic circuit
103
is operable in response to an external input signal during burn-in.
Conventional semiconductor integrated circuit
101
also includes a vector generator circuit
112
and a refresh counter and control circuit
106
. During burn-in operation, DRAM
102
can receive addresses, instructions, and data necessary for the burn-in operation from vector generator circuit
112
and refresh counter and control circuit
106
. In this way, DRAM
102
and logic circuit
103
can be made to operate independently and simultaneously, so that a burn-in time can be reduced.
Conventional semiconductor integrated circuit
101
also includes a multipexer
113
. Through multipexer
113
, vector generator
112
receives vector generation control signal MBICMD, write data initial values (DIN
0
to DINn), data inversion control signal DININV, read signal LDRD, and write signal LDWT. Write data initial values (DIN
0
to DINn) are signals that set the initial values of the write data. Data inversion control signal DININV, read signal LDRD, and write signal LDWT are signals for inputting a read/write command into vector generator circuit
112
. Vector generator circuit
112
also receives a carry signal RCRY generated by refresh counter and control circuit
106
.
Vector generator circuit
112
includes a column address generator circuit
114
, a segment address generator circuit
115
, a write data generator circuit
116
, a function command generator circuit
117
, and an address generation control circuit
118
.
Column address generator circuit
114
generates column address signals (CA
0
to CAn). Segment address generator circuit
115
generates segment address signals (S
0
to Sn). Write data generator circuit
116
generates write data signals (D
0
to Dn) based upon write data initial values (DIN
0
to DINn) and write signal LDWT. Function command generator circuit
117
generates read signal RD and write signal WT.
DRAM
102
receives column address signals (CA
0
to CAn), write data signal (D
0
to Dn), read signal RD, write signal WT, vector generation initiation signal MBI, and segment address signals (S
0
to Sn) from vector generator circuit
112
.
An input circuit
104
is provided on an input side of DRAM
102
. An output circuit
105
is provided on an output side of DRAM
102
. DRAM
102
also includes refresh counter and control circuit
106
and segment address decoder
107
. Refresh counter and control circuit
106
generates a refresh signal and includes an address counter for generating a row address for selecting a row or word line to refresh.
Segment address decoder
107
selects one segment among four memory segments (not shown) provided on DRAM
102
based on segment address signals (S
0
to Sn).
Conventional semiconductor integrated circuit
101
further includes logic circuit
103
. As previously mentioned, logic circuit
103
includes multiplexers (
108
to
111
). Multiplexers (
108
and
109
) are provided on an input side front stage of input circuit
104
of DRAM
102
. Multiplexers (
108
and
109
) each receive an input signal from input terminals (IN
1
to INn), respectively and another signal from within logic circuit
103
. Multiplexers (
110
and
111
) are provided on an output side next stage of output circuit
105
of DRAM
102
. Multiplexers (
110
and
111
) each receive an output signal from DRAM
102
and a signal from within logic circuit
103
and generate signals at output terminals (OUT
1
to OUTn), respectively.
During burn-in operation, vector generator circuit
112
and refresh counter and control circuit
106
generates addresses, instructions, and data for operating DRAM
102
based upon vector generation control signal MBICMD, write data initial values (DIN
0
to DINn), data inversion control signal DININV, read signal LDRD, and write signal LDWT. DRAM
102
is operated in accordance with those addresses, instructions, and data during the burn-in operation.
Along with a test mode signal TM, logic circuit
103
is also operated in response to vector generation control signal MBICMD, write data initial values (DIN
0
to DINn), data inversion control signal DININV, read signal LDRD, and write signal LDWT during burn-in operation.
In this way, DRAM
102
and logic circuit
103
are simultaneously operated during burn-in operation and burn-in test time is shortened.
As described above, in a burn-in operation of conventional semiconductor integrated circuit
101
, extra input signals may be needed. However, the greater the number of input signals, the more input/output pins are required in a semiconductor integrated circuit. A burn-in apparatus or tester can be limited by the number of input/output pins. This can be due to limited bandwidth, as just one example. During a burn-in test, many devices may be tested in parallel. By having a large number of functioning input/output pins per device, the bandwidth of the tester can be limited because it may not be desirable to test too many devices in parallel being controlled by the same signal lines due to increased loads and tester limitations.
Thus, it is desirable that the number of input signals needed in a burn-in test be reduced. This can allow costs to be decreased by allowing a larger number of semiconductor integrated circuits to be tested simultaneously.
Also, when a large number of input signals are used, such as in a conventional semiconductor integrated circuit, a large number of test patterns of input signals is increased and complexity is increased. This can increase test time and cost. It is preferable to reduce the number of patterns in order to decrease cost.
In view of the above discussion, it would be desirable to provide semiconductor device which may be capable of executing a burn-in operation in a memory and a logic circuit simultaneously without increasing the number of input signals inputed from the outside.
SUMMARY OF THE INVENTION
According to the present embodiments, a semiconductor integ

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