Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-20
2004-08-24
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S599000, C438S618000
Reexamination Certificate
active
06780745
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit (hereinafter called “IC”) and a method of manufacturing it, and particularly to a method of laying out respective circuit blocks which constitute the IC.
2. Description of the Related Art
A custom IC such as an ASIC (Application Specific Integrated Circuit) is normally designed by a gate array system, an embedded array system, a standard cell system or full custom system.
In an IC designed by the gate array system, layers other than a metal wiring layer are formed as master slices in advance and a plurality of basic cells are provided, followed by formation of wiring layers, whereby the basic cells are electrically connected to one another and circuit functions constituting a NAND circuit and an OR circuit can be implemented.
According to the standard cell system or full custom system, since dedicated macro cells such as a CPU, a RAM or the like comprised of pre-designed circuit blocks are used, the area of the IC chip can be less reduced. The use of a layout editor or the like in particular allows the attainment of the minimum area of the IC chip.
The embedded array system in contrast to the above-described gate array system, standard cell system and full custom system has the following characteristics. Namely, according to the embedded array system, dedicated macro cells such as a CPU, a RAM, etc. are embedded in a base array at a design state of an IC layout. In the embedded array system, a layer is provided in which functional elements or devices such as MOS transistors, etc. are formed by using a previously-designed and manufactured mask, and each of the wiring layers for interconnecting the plurality of functional devices with one another is formed over the layer in which the functional elements or devices are formed. Incidentally, each of the wiring layers is normally hereinafter called a “customized layer” because it is designed for each user. On the other hand, the layer in which the functional devices are formed, is hereinafter called a “non-customized layer” because it is used on a general-purpose basis.
Owing to the adoption of the embedded array system in this way, the design and fabrication of the mask for forming the non-customized layer are allowed even at a stage in which logic circuits other than the dedicated macro cells have not been determined. Thus, an IC is formed in a shorter turn around time (“TAT”) similar to that employed in the gate array system in which the logic circuits are implemented by the customized layer alone.
Even when it is necessary to change a logic circuit, only a change in customized layer allows for such a circuit change without a change in mask for forming the non-customized layer.
The layout of dedicated macro cells according to the embedded array system are designed in accordance with, for example, the standard cell system or full custom system. According to the full custom system, each dedicated macro cell is implemented in a narrow area as compared with the gate array system. Consequently, the chip area of the IC laid out by the embedded array system is smaller than that for an IC laid out by the pure gate array system.
In the gate array system on the other hand, the IC designed by the gate array system normally makes use of a large number of general-purpose functional devices so as to correspond to a plurality of specifications. Therefore, the chip area of the IC will spontaneously increase.
While the chip area of the IC designed by the standard cell system or full custom system is decreased as described above, the period from the completion of its design to the start of fabrication of all the layers of the IC is longer.
As those other than the dedicated macro cells, so-called design resources such as the macro cells and base array designed by the gate array system, etc. are used in the embedded array system. Since the macro cells designed by the gate array system have high general versatility corresponding to a plurality of specifications, they increase in scale as compared with the macro cells generally designed by the standard cell system or the full custom system. Accordingly, the chip area of the IC designed by the embedded array system increases as compared with that designed by the standard cell system or full custom system and hence this exerts a significant influence on the cost of the chip.
With the foregoing in view, it is therefore an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit, which is capable of reducing a chip area thereof and being designed and manufactured in a short period of time.
SUMMARY OF THE INVENTION
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor integrated circuit comprised of a plurality of functional blocks and a gate array block, each of these functional blocks respectively provided with predetermined functions by arbitrarily-placed semiconductor devices, the method comprising the following steps:
a first step for placing a gate array block comprised of a plurality of basic cells arranged in line and a plurality of functional blocks within a predetermined area of a semiconductor chip;
a second step for designing necessary circuits in the gate array block; and
a third step for electrically connecting between the gate array lying within the basic cell block by using interconnections.
According to the manufacturing method, circuits formed by the plurality of functional blocks are determined in the first step. Masks corresponding to the determined circuits can be designed and manufactured. Another step for determining a circuit corresponding to the basic cell block by using a gate array system can be executed in parallel with the design and fabrication of the masks. Thus, the time required to complete the semiconductor integrated circuit inclusive of the design and fabrication thereof can be reduced as compared with the case in which the design and manufacture of the masks are started after all the circuits have been determined.
The basic cell block and the plurality of functional blocks are may be laid out by a standard cell system. Alternatively, they may be laid out by a full custom system. According to the method referred to above, the semiconductor integrated circuit can be implemented by a chip having a small area.
If a plurality of basic gates are electrically connected to one another by metal wiring layers to construct the circuit for the basic cell block, then the circuit corresponding to the basic cell block in the second step is determined by principally designing the metal wiring layers. Namely, masks corresponding to metal wiring layers for electrically connecting between the functional blocks are designed and manufactured, and metal wiring layers for electrically connecting the basic cells lying within the basic cell block are formed using the masks in the second step, whereby all the circuits employed in the semiconductor integrated circuit are completed. According to the present method, the time required between the completion of the design of the semiconductor integrated circuit and the completion of the fabrication thereof substantially coincides with the time required to form the metal wiring layers. Thus, the period during which the semiconductor integrated circuit is completed, can be greatly reduced as compared with the prior art.
Further, one of the plurality of functional blocks can be formed as a CPU core block or memory cell block.
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Shoji Kimikatsu
Tadokoro Hirofumi
Yanaga Osamu
Anderson Chad C.
Crane Sara
Oki Electric Industry Co. Ltd.
Sartori Michael A.
Venable LLP
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