Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2003-01-17
2004-07-13
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S189120, C365S230080
Reexamination Certificate
active
06762969
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit using nonvolatile memory cells to store control information for defect relief, trimming of circuit characteristics or function switching with respect to a plurality of circuit modules, and a method of manufacturing a semiconductor integrated circuit with control information written into such nonvolatile memory cells. The present invention relates to, for example, a technology effective for application to a microcomputer or a system LSI equipped with a logic circuit and a RAM.
A technology for causing a nonvolatile memory cell like a flash memory cell to hold relief information or the like used for defect relief of an on-chip memory and a characteristic adjustment to a logic circuit has been described in Unexamined Patent Publication No. 2000-149588 (corresponding U.S. Pat. No. 2002/163840). According to it, relief information or the like for a defect of a RAM is stored in the flash memory in a semiconductor integrated circuit in which the RAM and the flash memory are implemented on a chip together with a CPU (Central Processing Unit). Further, the relief information or the like held in the flash memory is read into a general-purpose bus as part of an initializing operation at power-on or the like, and the read relief information or the like is loaded into a register inherent in the RAM or the like. The relief information or the like loaded into the register is supplied to a defective address determination circuit, a switching circuit for switching a defective address to a relief address, etc., in the corresponding RAM.
SUMMARY OF THE INVENTION
The present inventors have discussed control information for defect relief, trimming of circuit characteristics or function switching with respect to on-chip circuit modules.
Firstly, high reliability is required of the storage of such control information. When an error occurs in such control information even if only slightly, each circuit module causes a malfunction on a permanent basis or causes an undesired reduction in performance. When a flash memory used on a general-purpose basis upon an actual operation of an LSI is used in the retention of the control information at this time, reliability similar to reliability for general data can be merely obtained for the control information.
Secondly, when control information is initially set using a general-purpose bus, there is a need to provide a switching circuit for changing a configuration of connection of the general-purpose bus used even in an actual operation and each circuit module or a connecting destination in each circuit module, and control logic thereof. Moreover, control on the selection of a register corresponding to a destination to be loaded, addressing and the like is required to load control information into each circuit module by use of a common bus. In brief, a circuit configuration becomes relatively complex.
Thirdly, there is a need to avoid easy rewriting of such control information. Accordingly, address management of a system is also needed in such a manner that rewriting of the control information can be effected on the control information storage region of a flash memory available upon an actual operation in a privileged mode or a user nondisclosure mode alone.
Fourthly, if there is a need to write control information into the flash memory in each case when the confirmation of operation by control information is performed, the frequency of rewriting increases due to the operation confirmation, and hence there is a possibility that characteristic deterioration is incurred in each nonvolatile memory cell.
An object of the present invention is to provide a semiconductor integrated circuit capable of assuring high reliability with respect to control information delivered for defect relief, trimming of circuit characteristics or function switching for a plurality of on-chip circuit modules.
Another object of the present invention is to provide a semiconductor integrated circuit capable of simplifying a circuit configuration necessary for delivery of control information for defect relief, trimming of circuit characteristics or function switching.
A further object of the present invention is to provide a semiconductor integrated circuit which lessens a possibility that a rewrite operation will be undesirably effected on control information for defect relief, trimming of circuit characteristics or function switching.
A still further object of the present invention is to provide a semiconductor integrated circuit capable of reducing to a minimum, the frequency of rewriting of each nonvolatile memory cell in order to perform operation confirmation by control information for defect relief, trimming of circuit characteristics or function switching.
A still further object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit, which enhances reliability of an operation based on control information for defect relief, trimming of circuit characteristics or function switching.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor integrated circuit according to the present invention has a plurality of circuit modules connected to a first wiring such as a common bus or the like and includes a fuse circuit which has a plurality of nonvolatile memory cells respectively storing control information for defect relief, trimming of circuit characteristics or function switching with respect to the plurality of circuit modules and which allows memory information to be electrically read therefrom. A plurality of volatile register circuits provided with a plurality of volatile memory cells to store the control information therein are adopted in association with the plurality of circuit modules every the plurality of circuit modules. The fuse circuit and the plurality of register circuits are connected by a dedicated second wiring for the purpose of transfer of the control information. A control circuit is provided which controls application of an operating voltage to each of the nonvolatile memory cells to enable reading of memory information from the fuse circuit, controls the transfer of the control information read from the fuse circuit to each of the register circuits through the second wiring, and performs control for releasing application of the operating voltage to each of the nonvolatile memory cells after reading of the control information from the fuse circuit to the second wiring.
In a further detailed one aspect of a semiconductor integrated circuit according to the present invention, a first register circuit is provided which includes a plurality of volatile memory cells for holding the control information read from the fuse circuit. The first register circuit and a plurality of second register circuits are respectively connected by the second wiring dedicated for the transfer of the control information. At this time, a control circuit performs control on application of a voltage enabling reading of the memory information from each of the nonvolatile memory cells of the fuse circuit to the nonvolatile memory cell, control on the transfer of the control information read from the nonvolatile memory cells to the first register circuit to the second register circuits through the second wiring, and control for releasing the application of the voltage enabling the reading of the memory information from the nonvolatile memory cells to the nonvolatile memory cells after the reading of the control information into the first register circuit.
According to the above means, each nonvolatile memory cell of the fuse circuit unsharing the first wiring like the common bus is used to store control information. Thus, it is possible to suppress deterioration in the reliability of storage of the
Sasaki Toshio
Yamada Toshio
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Nguyen Viet Q.
Reed Smith LLP
Renesas Technology Corporation
LandOfFree
Semiconductor integrated circuit and method of manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and method of manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and method of manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3224006