Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-01-24
2003-04-01
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S101000, C257S204000, C257S205000, C257S206000, C257S368000, C257S401000
Reexamination Certificate
active
06542005
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a large scale integrated circuit (LSI) and a method of designing the same, and in particular, a semiconductor integrated circuit, in which clock skew is suppressed, and a method of designing the same.
2. Description of the Related Art
An LSI chip is provided with a core region (internal circuit) for various processing in synchronization with clock signals and an input/output circuit region for transmitting and receiving signals between the core region and the outside. In the core region, a plurality of flip-flop groups and a clock tree consisting of clock drivers in a plurality of stages for distributing the clock signals to these flip-flop groups.
FIG. 1A
is a schematic view showing a transistor composing a conventional clock driver, and
FIG. 1B
is a schematic view showing a transistor composing a flip-flop group.
In a conventional LSI or the like, as shown in
FIGS. 1A and 1B
, a transistor composing a clock driver is provided with a gate electrode
51
and source drain diffusion layers
52
, and a transistor composing a flip-flop group is provided with a gate electrode
53
and source drain diffusion layers
54
. The gate lengths of the gate electrodes
51
and
53
are equal to each other in design, for example, “L”.
However, in actual processing, it is extremely difficult to completely prevent dispersion in the gate lengths in the process of etching or the like, so that the clock driver and the flip-flop group have dimensional differences of the same degree to each other.
FIGS. 2A and 2B
shows transistors in a case where the dimensional differences make the gate lengths longer in a conventional LSI, wherein
FIG. 2A
is a schematic view showing a transistor composing a clock driver, and
FIG. 2B
is a schematic view showing a transistor composing a flip-flop group.
FIGS. 3A and 3B
show transistors in a condition where the gate lengths become shorter due to the dimensional differences in a conventional LSI, wherein
FIG. 3A
is a schematic view showing a transistor composing a clock driver, and
FIG. 3B
is a schematic view showing a transistor composing a flip-flop group.
If the gate lengths become longer by “&Dgr;L”, due to a dimensional difference, both the gate lengths of the transistor composing a clock driver and the transistor composing a flip-flop group are “L+&Dgr;L” as shown in
FIGS. 2A and 2B
. Therefore, both the relative errors in these gate lengths are “&Dgr;L/L”.
On the other hand, if the gate lengths become shorter by “&Dgr;L” due to dimensional differences, both the gate lengths of the transistor composing a clock driver and the transistor composing a flip-flop group are “L−&Dgr;L” as shown in
FIGS. 3A and 3B
. Therefore, in this case, the relative errors in these gate lengths are also “&Dgr;L/L”.
If such unevenness in the gate lengths occurs, clock skew described below occurs.
FIG. 4
is a timing chart showing clock skew between two flip-flop groups. Herein, gate lengths in a first flip-flop group and a clock driver which transmits a clock signal CLK
1
to the first flip-flop group have been “L−&Dgr;L”, and gate lengths in a second flip-flop group and a clock driver which transmits a clock signal CLK
2
to the second group have been “L+&Dgr;L”.
Generally, in a case where the gate width is constant, when the gate length becomes longer, the drive capability of the transistor lowers, and delay time of the clock signal becomes greater. Therefore, the clock signal CLK
1
is transmitted to the first flip-flop group more quickly than the designed time, and the clock signal CLK
2
is transmitted later than the designed time. As a result, as shown in
FIG. 4
, clock skew occurs between the two clock signals CLK
1
and CLK
2
.
If such an influence of clock skew becomes greater, the first and second flip-flop groups cannot simultaneously operate. Therefore, in such an LSI, the period of the clock signal must be increased to a degree at which the influence of clock skew can be ignored, which inevitably results in a lowering of the operation speed by lowering the frequency.
Such problems caused by clock skew are remarkable when the gate length is shortened to approximately 0.18 &mgr;m and the frequency of the LSI is increased to approximately 200 MHz, so that further reduction in the gate length and further increase in the speed of the LSI are difficult.
In Japanese Unexamined Patent Publication No. Hei 9-331238, a semiconductor integrated circuit is disclosed in which the gate length of a specific transistor composing a pulse generation circuit is made long in order to prevent unevenness in the standard pulse widths with respect to unevenness in the gate lengths. However, in this conventional semiconductor integrated circuit, clock skew caused by dispersion in manufacturing cannot be suppressed although fluctuation in the pulse width can be suppressed.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor integrated circuit which can suppress clock skew due to dispersion in manufacturing and a method of designing the same.
According to one aspect of the present invention, a semiconductor integrated circuit comprises logic circuits and a clock tree including clock drivers. The logic circuits have transistors. The clock drivers also have transistors to distribute a clock signal to the logic circuits. Gate lengths of the transistors provided in the clock drivers are longer than that of the transistors provided in the logic circuits.
In the invention, since the gate length of the transistor provided in the clock driver is made longer than that of the transistor provided in the logic circuit, even if the gate lengths become uneven in the process of etching or the like in the manufacturing process, the relative error in the gate length of the transistors in the clock driver can be made smaller than that of the transistor in the logic circuit. Therefore, the unevenness in the drive capability between the clock drivers can be suppressed. As a result, clock skew due to dispersion in manufacturing between the logic circuits connected to a distal end of the clock tree is suppressed.
Another aspect of the present invention, a method of designing a semiconductor integrated circuit which has logic circuits which have transistors and a clock tree including clock drivers which have transistors, the clock drivers distributing a clock signal to the logic circuits, the method comprises the step of setting gate lengths of the transistors provided in the clock drivers so as to be longer than that of the transistors provided in the logic circuits.
REFERENCES:
patent: 4588903 (1986-05-01), Johnson
patent: 5285096 (1994-02-01), Ando et al.
patent: 5914516 (1999-06-01), Konno
patent: 6053950 (2000-04-01), Shinagawa
patent: 6090650 (2000-07-01), Dabral et al.
patent: 6092211 (2000-07-01), Hozumi
patent: 3-034365 (1991-02-01), None
patent: 404027155 (1992-01-01), None
patent: 9-331238 (1997-12-01), None
patent: 10-340957 (1998-12-01), None
patent: 11-068046 (1999-03-01), None
Katten Muchin Zavis & Rosenman
Tan Vibol
Tokar Michael
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