Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-18
2002-11-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S030000, C714S731000, C714S733000, C714S744000, C711S101000, C326S016000, C326S101000, C326S093000, C365S201000, C365S072000, C327S520000, C327S565000
Reexamination Certificate
active
06484294
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit for testing logic circuits and a method for designing a circuit for performing such tests.
BACKGROUND ART
Generally, logic circuits that operate at high speeds each include an additional test circuit called a scan circuit for readily testing the logic circuit in question. Because the scan circuit runs on a scan clock, i.e., on a clock signal for testing purposes, tests cannot be conducted on a system clock (design frequency) on which the logic circuit normally operates. Tests performed by use of the system clock on which the logic circuit usually runs are called delay tests. For enhanced reliability, the delay tests must be carried out.
Japanese Patent Laid-open No. Hei 4-118570 discloses flip-flops for executing delay tests, the flip-flops being arranged to store system data in keeping with a system clock, accommodate scan data by use of a scan clock, and store scan data based on the system clock. In operation, the flip-flops are connected to an input and an output terminal of each circuit path under test. With the system clock in use, the flip-flop at the input terminal reads scan data while the flip-flop at the output terminal acquires system data in keeping with the system clock.
There exists a method for performing delay tests on the logic circuit through the use of not a specifically added circuit but function test patterns that have been created using a string of operating instructions. The method involves having the function test patterns entered through external input pins of the logic circuit to get the logic circuit running on the system clock, before output patterns are acquired through output pins of the circuit. Delay tests are carried out by making comparisons between output patterns obtained beforehand through logic simulations or the like on the one hand, and patterns that are output when the logic circuit in question is operated on the other hand.
The above-cited known techniques have the following major problems:
First of all, there is a lack of consideration for arranging the flip-flops in a manner suitable for performing the delay tests discussed in the publication. To execute the delay tests requires using flip-flops capable of storing system data in keeping with the system clock, retaining scan data based on the scan clock, and accommodating scan data by use of the system clock. Such flip-flop arrangements tend to have a large scale of circuitry. If the flip-flops are connected to all input and output terminals of the circuit under test, the whole circuit area will become inordinately large.
As a second disadvantage, the flip-flops must be initialized using the scan clock, scan data must be input to the paths under test, and the results of having passed data through the paths under test must be acquired before the delay tests can be conducted. The scan clock and system clock must be switched during a single system clock cycle by use of a switching signal. If the circuit under test is large enough in scale and if flip-flops are connected to all paths to be tested, delays in the propagation of the switching signal can prevent the system clock and scan clock from getting switched during the single clock cycle. The clock switchover can also be thwarted if the clock period is sufficiently short.
It is therefore an object of the present invention to overcome the above and other deficiencies of the prior art and to provide a semiconductor integrated circuit capable of permitting delay tests while minimizing any increase in its circuit area. It is another object of the invention to provide a semiconductor integrated circuit allowing highly accurate delay tests to be carried out.
DISCLOSURE OF INVENTION
In achieving the foregoing and other objects of the present invention and according to one aspect thereof, there is provided a semiconductor integrated circuit constituted by a logic circuit made of logic elements, by scanning function-equipped storage elements, and delay test-ready scanning function-equipped storage elements. The scanning function-equipped storage elements store system data based on a system clock and retain scan data in keeping with a scan clock. The delay test-ready scanning function-equipped storage elements store system data by use of the system clock and accommodate scan data based on the scan clock or system clock. When the semiconductor integrated circuit includes the scanning function-equipped storage elements and the delay test-ready scanning function-equipped storage elements, the logic circuit is tested on the basis of the system clock with a reduced number of delay test-ready scanning function-equipped storage elements. This structure helps prevent the circuit area from expanding.
According to another aspect of the invention, there is provided a semiconductor integrated circuit constituted by a logic circuit made of logic elements and by delay test-ready scanning function-equipped storage elements capable of internally switching a system clock and a scan clock for storing scan data. When the system clock and scan clock are internally switched, there is no need to have a switching signal input from the outside; hence no need for the conventional switching signal wiring. This makes it unnecessary to consider delay times of switching signal propagation in the presence of a plurality of delay test-ready scanning function-equipped storage elements. This structure allows highly accurate tests to be conducted while preventing the circuit area from getting larger.
According to a further aspect of the invention, there is provided a method for designing a semiconductor integrated circuit constituted by a logic circuit made of a plurality of logic elements and by a plurality of scanning function-equipped storage elements, wherein the likelihood of a transition signal occurring on an output signal line of each scanning function-equipped storage element is obtained every time a system clock signal is applied to the scanning function-equipped storage element in question, the obtained likelihood being used as a basis for determining which of the plurality of scanning function-equipped storage devices may be changed.
In one preferred variation of the semiconductor designing method according to the invention, the changeable scanning function-equipped storage elements may be utilized as delay test-ready scanning function-equipped storage elements constituting a semiconductor integrated circuit. When this preferred method is adopted, there is no need to assign the delay test-ready scanning function-equipped storage elements to all outputs of the logic circuit. This helps prevent the circuit area from expanding.
In another preferred variation of the semiconductor designing method according to the invention, the number of changeable scanning function-equipped storage elements may be varied as desired or depending on the rate of error detection. When this preferred method is employed, the exact number of delay test-ready scanning function-equipped storage elements may be determined as required by the designer for the tests involved.
In a further preferred variation of the semiconductor designing method according to the invention, circuit data may be output to represent delay test-ready scanning function-equipped storage elements, scanning function-equipped storage elements and a logic circuit which constitute a semiconductor integrated circuit designed by the method. Using the output circuit data, other designers may also design semiconductor integrated circuits that have a reduced circuit area.
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Hatayama Kazumi
Hotta Takashi
Kiyoshige Yoshikazu
Nakao Michinobu
Hitachi , Ltd.
Kenyon & Kenyon
Kik Phallaka
Siek Vuthe
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