Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-05-24
2001-11-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S185250, C365S149000, C365S189011
Reexamination Certificate
active
06324113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of memory cells including capacitors, and a method of controlling the same. In particular, the present invention relates to a semiconductor integrated circuit for automatically performing refresh operations to the memory cells and a method of controlling the same.
2. Description of the Related Art
In general, the semiconductor integrated circuits known as having a plurality of memory cells including capacitors include dynamic random access memories (DRAMs). DRAMs are suited for higher integration since their memory cells can be made in smaller configurations. The DRAMs, however, require refresh operations in order to retain data stored in the memory cells.
Meanwhile, the semiconductor integrated circuits known as aimed at both the usability of static RAMs (SRAMs) and the high integration of DRAMs include pseudo SRAMs (PSRAMs) and virtual SRAMs. PSRAMs and virtual SRAMs comprise controlling circuits for refresh operation and memory cores similar to those of DRAMs.
Pseudo SRAMs receive a refresh signal from the exterior, generate refresh addresses within the chips, and perform refresh operations to their memory cells. The pseudo SRAMs are detailed in NIKKEI ELECTRONICS 1986.9.22(no.404) pp.199-217, Nikkei business publications.
Virtual SRAMs incorporate the time required for refresh operations into read cycles and write cycles so that the performances of the refresh operations do not show to the exterior. The virtual SRAMs are detailed in TOSHIBA REVIEW vol.41, no.3, 1986, pp.227-230 (TOSHIBA KK).
Now, in the case where a pseudo SRAM performs refresh operations during intervals between read and write operations, refresh signals must be supplied thereto from the exterior. Therefore, the system using a pseudo SRAM needs to have some controlling circuits such as a refresh timer mounted on its printed-wiring board. Besides, the refresh operations have to be taken into consideration for the circuit design and timing design of the system.
In a virtual SRAM, the cycle times required for read and write operations need to be longer than their actual values by the time required for a refresh operation. This leads to a problem of greatly extended access time.
Accordingly, although both types of the memories are aimed at the usability of SRAMs, their operation cannot be identical to that of SRAMs. Besides, it is not possible not to show their performances of refresh operations completely to the exterior of the chips.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit and a method of controlling the same in which the performance of a refresh operation does not show to the external system.
According to one of the aspects of a semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises: a pair of memory cores each having a plurality of memory cells including capacitors, having written identical data; a refresh signal generating circuit; a refresh controlling circuit; and a read controlling circuit.
The refresh signal generating circuit generates a refresh signal for retaining the data written in the memory cells. The refresh controlling circuit supplies the refresh signal to one of the memory cores and operates the memory core during a predetermined period as a refresh core for performing refresh and write operations. The read controlling circuit supplies a read signal for reading the data from the memory cells, to one of the memory cores not supplied with the refresh signal and operates the memory core as a read core for performing read and write operations.
That is, a pair of memory cores is operated as refresh cores for performing a refresh operation during each predetermined period, and a read core for performing a read operation. Therefore, the read operation is performed in the read core without waiting when the read signal is supplied during a refresh operation. Consequently, the refresh operation, even in conflict with the read operation, is automatically performed and the performance does not show to the external system so that the system need not control the refresh operation. This enables users to use the semiconductor integrated circuit without taking a refresh operation into consideration.
Write cycle time defined as an operation specification, is set longer than the actual time necessary for each of the memory cores to perform a write operation. The sum of each time difference between each write cycle and write operation during a plurality of write cycles create a predetermined time margin. This time margin is utilized to perform a refresh operation so that the performance of the refresh operation in conflict with the write operation does not show to the external system. In other words, the data in the memory cores is not damaged even when a write operation is performed throughout the refresh core period.
According to another aspect of the semiconductor integrated circuit in the present invention, the predetermined period where the memory core operates as the refresh core, is set so that the sum of each time difference between each write cycle and write operation is equal to or longer than a refresh cycle period. Therefore, the refresh cycle can be reliably performed during the refresh core.
According to another aspect of the semiconductor integrated circuit in the present invention, a write holding circuit provided in each of the memory cores holds a write signal for use in a write operation on the memory cells.
The write signal supplied to the memory core during a refresh operation is held in the write holding circuit. The write operation of the write signal held in the write holding circuit is performed after the completion of the refresh operation. Subsequently, the write holding circuit holds the write signals supplied in sequence and the write operations are performed by using the held signals. The time difference between each write cycle and write operation is gradually accumulated in each write operation. In other words, the time taken for performing the refresh operation prior to the write operation is compensated by the time margins in the subsequent write cycles. Thus, the performance of the refresh operation in conflict with the write operation does not show to the external system so that the system need not control the refresh operation.
According to another aspect of the semiconductor integrated circuit in the present invention, the write holding circuit comprises the predetermined number of holding parts. Therefore, the time taken for performing a refresh operation prior to the write operation is reliably compensated by the time margins in the subsequent write cycles.
According to another aspect of the semiconductor integrated circuit in the present invention, a refresh holding circuit provided in each of the memory cores holds a refresh signal generated by are fresh signal generating circuit. When the refresh signal is supplied during a write operation, the refresh holding circuit temporarily holds the refresh signal. After the completion of the write operation, the held refresh signal is used to perform a refresh operation.
According to another aspect of the semiconductor integrated circuit in the present invention, each of the memory cores is cyclically operated as the refresh core, thereby preventing the data retained in the memory cells from being damaged.
According to another aspect of the semiconductor integrated circuit in the present invention, by performing a refresh operation at the beginning of its period where the memory core operates as the refresh core, the time taken for performing the refresh operation is gradually compensated by the time margins in the subsequent write cycles, which are the time differences between the write cycles and the write operations. Thus, the performance of the refresh operation in conflict with the write operation does not show to the external system so that the system need not co
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nelms David
Yoha Connie C.
LandOfFree
Semiconductor integrated circuit and method of controlling same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and method of controlling same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and method of controlling same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2598395