Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-06-14
2004-07-20
Gossage, Glenn (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000
Reexamination Certificate
active
06766408
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit such as a single chip microcomputer (hereinafter referred to as a microcomputer) having a built-in non-volatile memory such as a flash memory, an electronically erasable programmable read only memory (hereinafter referred to as EEPROM), an erasable programmable read only memory (hereinafter referred to as EPROM), or a ferroelectric random access memory (hereinafter referred to as FeRAM), and a central processing unit (hereinafter referred to as “CPU”) or gate array. In particular, the present invention relates to a semiconductor integrated circuit which has no work random access memory (hereinafter referred to as RAM) and which is capable of executing programs. The invention further relates to a method for writing into a non-volatile memory incorporated in such semiconductor integrated circuits.
BACKGROUND ART
Previously, semiconductor integrated circuits having a CPU and a non-volatile memory incorporated therein have been mounted on a board and then a ROM writer communicates with the CPU through a serial interface to operate the CPU for writing programs into the non-volatile memory or updating them. This is called “on-board (in-circuit) writing”. As an example,
FIG. 6
depicts an example of the circuit configuration for on-board writing.
In
FIG. 6
, a microcomputer
300
is formed of a CPU core
301
, a control register
302
, a synchronous serial communication interface
303
, a multiplexer
304
, a flash memory
305
, and a mask ROM
307
. The CPU core
301
is connected to the mask ROM
307
and the multiplexer
304
through an instruction address bus B
31
and an instruction bus B
32
. Additionally, the CPU core
301
is connected to the control register
302
, the synchronous serial communication interface
303
, and the multiplexer
304
through a data address bus B
33
and a data bus B
34
.
The multiplexer
304
is connected to the flash memory
305
through a bus B
35
. The flash memory
305
is a non-volatile memory for storing instruction codes that the CPU core
301
should execute or data that the CPU core
301
uses.
When a program is written into the flash memory
305
, a ROM writer
400
is connected to the synchronous serial communication interface
303
. The ROM writer
400
transfers operation commands, address information or data by synchronous serial communications. On the other hand, the mask ROM
307
incorporated in the microcomputer
300
is a read-only memory for storing programs executed by the CPU core
301
to perform on-board writing to the flash memory
305
, and the mask ROM
307
is used for communications and sequencing. The operation commands that have been transferred from the ROM writer
400
to the microcomputer
300
are executed by the on-board writing program stored in the mask ROM
307
and erasing or data writing is peformed based on the address information. Management during writing or erasing is also performed by the programs stored in the mask ROM
307
.
Synchronous serial communication uses a CLK signal line
404
for transmitting clocks from the ROM writer
400
to the microcomputer
300
a RXD signal line
401
for transmitting data from the ROM writer
400
to the microcomputer
300
, a TXD signal line
402
for transmitting data from the microcomputer
300
to the ROM writer
400
, and a SCLK signal line
403
for transmitting and receiving serial clocks between the ROM writer
400
and the microcomputer
300
.
The control register
302
is connected to the CPU core
301
as described above, and is also connected to the multiplexer
304
through a flash memory writing address bus B
36
, a flash memory writing data bus B
37
, and a control signal bus B
38
. The control register
302
holds data written by the CPU core
301
and outputs the data to the flash memory writing address bus B
36
, the flash memory writing data bus B
37
, and the control signal bus B
38
.
The multiplexer
304
is connected to the CPU core
301
and the flash memory
305
as described above, and is also connected to a switch
308
through a flash memory writing mode designating line
306
. The switch
308
is turned on (closed) to ground the flash memory writing mode designating line
306
when on-board writing is conducted, and it is turned off (opened) to pull up the flash memory writing mode designating line
306
through the pull up resistor when on-board writing is not conducted. The multiplexer
304
connects the buses B
31
to B
34
with the bus B
35
when the flash memory writing mode designating line
306
is pulled up, while it connects the buses B
36
to B
38
with the bus B
35
when the flash memory writing mode designating line
306
is grounded.
Next, the normal operation (an operation other than on-board writing) of the microcomputer
300
shown in
FIG. 6
will be described. In addition, during normal operation, the switch
308
is turned off (opened) and the flash memory writing mode designating line
306
is pulled up.
First, the CPU core
301
outputs an instruction address on the instruction address bus B
31
. The multiplexer
304
transmits the instruction address outputted on the instruction address bus B
31
to the bus B
35
. The flash memory
305
receives the instruction address from the bus B
35
and outputs an instruction code corresponding to the address to the bus B
35
. The multiplexer
304
transmits the instruction code outputted on the bus B
35
to the instruction bus B
32
. The CPU core
301
receives the instruction code from the instruction bus B
32
and executes the instruction code. In this manner, the CPU core
301
executes a series of instruction codes (a program) stored in the flash memory
305
.
Next, an on-board writing operation in the conventional example will be described. When on-board writing is performed, an on-board writing operator turns on (closed) the switch
308
and a power supply of the micro computer
300
, and also turns on a power supply of the ROM writer
400
to start the operation.
When the on-board writing operation is started, the CPU core
301
outputs an address corresponding to the on-board writing program I the mask ROM
307
to the instruction address bus B
31
. Then, the CPU core
301
reads the instruction codes for on-board writing from the mask ROM
307
through the instruction bus B
32
. Subsequently, the CPU core
301
executes the read instruction codes for on-board writing. The CPU core
301
further receives data and the like required for on-board writing from the ROM writer
400
through synchronous serial communication lines
401
to
404
and the synchronous serial communication interface
303
. In this manner, the CPU core
301
executes a series of instruction codes (a program) for on-board writing stored in the mask ROM
307
, whereby writing the flash memory
305
is performed.
Accordingly, because the mask ROM is needed to store programs for executing communication and sequencing for on-board writing, the size of the circuit has been increased. In particular, the microcomputer has suffered from a problem in that as the chip area for incorporating the mask ROM increases, the number of terminals also increases.
Additionally, to change the pulse width of each control signal or the number of retries while performing on-board writing, programs stored in the mask ROM need to be altered. In regard to this, it can be considered that programs in the mask ROM are created beforehand to output each of the control signals with multiple kinds of pulse widths. However, there has been a problem in that as the program size increases, the mask ROM size also increases.
As a method for solving such problems, it can be considered that programs for on-board writing are stored in the RAM and executed. However, a
4
-bit microcomputer is generally configured to have no work RAM. Besides, even when the RAM is included, the
4
-bit microcomputer or the like has varying data widths and instruction widths and thus it has been difficult to store the programs for on-board writing in the RAM and to execute them.
Gossage Glenn
Seiko Epson Corporation
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