Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-09-20
2002-11-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Resistor
C365S189050, C365S189011, C365S189050
Reexamination Certificate
active
06479363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method for testing the circuit. More particularly, the invention relates to a semiconductor integrated circuit structured so as to undergo tests in a shorter time with higher precision than before, as well as to a method for testing such a semiconductor integrated circuit.
2. Description of the Background Art
In recent years, ever-increasing functionality of system applications has entailed a growing capacity of built-in memories in semiconductor integrated circuits. In turn, the greater memory capacity in each semiconductor integrated circuit tends to increase the number of I/O pins for writing and reading data to and from the circuit in a concurrent and parallel manner. In order to counter such trends and to speed up tests on semiconductor integrated circuits, techniques have been proposed which utilize a single representative pin to test concurrently a plurality of memory cell arrays.
FIGS. 9A and 9B
illustrate how a conventional semiconductor integrated circuit is typically tested. More specifically,
FIG. 9A
is a block diagram showing a procedure for inputting data through a representative pin DQ
0
and writing the input data to a plurality of memory cell arrays CELL
0
through CELL
3
of a conventional semiconductor integrated circuit.
FIG. 9B
is a block diagram depicting a procedure for outputting via the representative pin DQ
0
signals indicative of states of the multiple memory cell arrays CELL
0
through CELL
3
in the conventional semiconductor integrated circuit.
As shown in
FIG. 9A
, the conventional semiconductor integrated circuit typically has I/O pins DQ
0
through DQ
3
corresponding to the memory cell arrays CELL
0
through CELL
3
. The I/O pins DQ
1
, DQ
2
and DQ
3
are furnished with I/O buffers
10
respectively. The I/O buffers
10
are fed with a control signal TCTRL through an inverter
12
. The signal TCTRL is held on the Low level in normal mode and raised to the High level in test mode. The I/O buffers
10
are kept active when the signal TCTRL is Low (i.e., in normal mode) and deactivated when the signal TCTRL is brought High (in test mode). That is, no signal is allowed to be input or output through the pins DQ
1
, DQ
2
and DQ
3
in test mode. The representative pin DQ
0
is provided with an I/O buffer
11
designed to remain active at all times. This means that signals are allowed to be input and output through the pin DQ
0
both in normal mode and in test mode.
A selector
14
is interposed between the memory cell array CELL
0
and the pin DQ
0
. The selector
14
has two paths: a normal path for ensuring direct conduction between the pin DQ
0
and the memory cell array CELL
0
, and a test input path for connecting the pin DQ
0
to the memory cell arrays CELL
0
through CELL
3
by way of a buffer circuit
16
. If the signal TCTRL is Low (i.e., in normal mode), the selector
14
conducts the normal path alone; if the signal TCTRL is High (in test mode), the selector
14
blocks the normal path and conducts the test input path. The signal TCTRL is also fed to the buffer circuit
16
. The buffer circuit
16
remains inactive when the signal TCTRL is Low (in normal mode) and is activated when the signal TCTRL is brought High (in test mode). This means that in test mode, data input through the pin DQ
0
are fed equally to all multiple memory cell arrays CELL
0
through CELL
3
.
As depicted in
FIG. 9B
, the selector
14
is connected to an output terminal of a coincidence detection circuit
18
. The coincidence detection circuit
18
is made up of an exclusive-OR circuit having four input terminals connected to the memory cell arrays CELL
0
through CELL
3
. Only when data from the memory cell arrays CELL
0
through CELL
3
coincide with one another does the coincidence detection circuit
18
effect a High-level output. In addition to the normal path and test input path discussed above, the selector
14
has a test output path which allows the coincidence detection circuit
18
and the pin DQ
0
to conduct when the signal TCTRL is driven High (in test mode). This means that in test mode, the pin DQ
0
receives a signal indicating whether data from the memory cell arrays CELL
0
through CELL
3
coincide with one another.
When the conventional semiconductor integrated circuit outlined above is in use, the signal TCTRL is first brought High to initiate test mode. Then common data are written to all memory cell arrays CELL
0
through CELL
3
by feeding the data to the pin DQ
0
for the write operation. A subsequent read operation using an output signal from the pin DQ
0
makes it possible to check whether the same data are output from the memory cell arrays CELL
0
through CELL
3
. As described, the conventional semiconductor integrated circuit permits multiple memory cell arrays CELL
0
through CELL
3
to be tested efficiently by use of a single representative pin DQ
0
.
One disadvantage of the conventional semiconductor integrated circuit above is that the pin DQ
0
receives a signal reflecting the retrieved data coinciding or not coinciding with one another regardless of the High or Low level of the data written to the memory cell arrays CELL
0
through CELL
3
in test mode. In other words, if the pin DQ
0
is set to become High when retrieved data coincide with one another, then the pin DQ
0
always gets the High-level signal upon data coincidence regardless of the level of the data written in the arrays CELL
0
through CELL
3
.
In normal mode, the conventional semiconductor integrated circuit transfers signals over a path ranging either from the memory cell array CELL
0
to the selector
14
to the pin DQ
0
, or from the arrays CELL
1
through CELL
3
to the pins DQ
1
through DQ
3
. In test mode, the circuit transfers signals over a path ranging from the memory cell arrays CELL
0
through CELL
3
to the coincidence detection circuit
18
to the selector
14
to the pin DQ
0
. That is, the conventional semiconductor integrated circuit has different signal transfer paths between normal mode and test mode.
In order to measure precisely the time in which to access individual memory cell arrays, it is preferred that relations between data stored in the memory cell arrays on the one hand and signals output to the I/O pins on the other hand remain the same both in normal mode and in test mode. For exact measurement of access times, it is also desired that the signal transfer path be the same in normal mode and in test mode. The conventional test method described above is deficient in these respects and thus inadequate to obtain accurate access times.
There is an additional problem of access delay. The conventional semiconductor integrated circuit transfers signals from the memory cell array CELL
0
to the pin DQ
0
through the selector
14
in normal mode, but sends signals from the memory cell arrays CELL
1
through CELL
3
directly to the pins DQ
1
through DQ
3
in normal mode. Because of that setup, an access delay develops only at the pin DQ
0
in normal mode of the conventional semiconductor integrated circuit.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to overcome the above and other deficiencies of the prior art and to provide a semiconductor integrated circuit having numerous memory cell arrays which are tested in a short time so that the time in which to access the arrays is measured precisely, with no access delay detected on any of I/O pins of the circuit.
It is a second object of the present invention to provide a test method for testing precisely in a short time a semiconductor integrated circuit comprising a large number of memory cell arrays.
The above objects of the present invention are achieved by a semiconductor integrated circuit having a facility for concurrently checking a plurality of output signals. The semiconductor integrated circuit includes a coincidence detection circuit for checking whether a plurality of output signals coincide with one another. The se
Berry Renee R.
McDermott & Will & Emery
Nelms David
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