Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-08-29
2004-06-22
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S038000, C326S101000
Reexamination Certificate
active
06753702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a master slice type semiconductor integrated circuit in which various logic circuits are formed by commonly carrying out product steps except a wiring step, and changing only the wiring step.
2. Description of the Related Art
Conventionally, a semi-custom designing method is known, as a technique for designing a semiconductor integrated circuit such as LSI and the like, in a short time. In particular, this method includes a master slice method in which a master slice containing a cell having a basic level function, such as a logic gate, a flip-flop and the like, is prepared in advance, and a user then determines a wiring pattern in accordance with an individually given logic circuit and attains a desirable semiconductor integrated circuit.
FIG. 1A
is a plan view showing a chip structure of the conventional master slice type semiconductor integrated circuit, and
FIG. 1B
is a plan view in which a transistor cell of the semiconductor integrated circuit of
FIG. 1A
is enlarged. A semiconductor integrated circuit
101
of the conventional master slice type has the array structure in which transistor cells
102
of the same dimension having the structure shown in
FIG. 1B
are arranged as a matrix on a chip. In
FIG. 1B
, a reference number
103
denotes a gate electrode, and a reference number
104
denotes a diffusion layer.
Also, in the conventional master slice type semiconductor integrated circuit, a clock signal is distributed to respective circuits on the chip by using a tree structure of a clock buffer referred to as a clock tree.
FIG. 2
is a plan view showing a clock distributing method in the conventional master slice type semiconductor integrated circuit.
In the tree structure of the clock buffer, a clock signal CLK is distributed from a first clock buffer
105
at a center to a plurality of second clock buffers
106
, and the clock signal CLK is distributed from the second clock buffer
106
to a plurality of third clock buffers
107
. Moreover, the clock signal CLK is distributed from the third clock buffer
107
to a circuit
108
, such as a flip-flop circuit and the like. A sequential circuit and a combinational circuit are freely placed on the chip. A clock phase number is also distributed, as necessary, by using the tree structure.
Another master slice type semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-188397).
FIG. 3
is a plan view showing a chip structure of the master slice type semiconductor integrated circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-188397). This semiconductor integrated circuit
201
has the structure in which an inner core area A is divided into a plurality of basic cell areas D by forming the inner core area A where basic cells are arranged as a matrix on a chip and further forming a cell area C dedicated to a sequential circuit. A clock buffer having high driving ability is formed in the cell area C dedicated to the sequential circuit, and the respective basic cells are formed adjacently to positions at which they can be connected at the shortest distance. Also, a combinational circuit besides the sequential circuit and the like are placed in an area E within the basic cell area D.
In the master slice type semiconductor integrated circuits shown in
FIGS. 1 and 2
, the sequential circuits are placed at random. Thus, the numbers of the sequential circuits connected to the respective clock buffers and the wiring lengths from the clock buffers to the sequential circuits are different, which brings about the situation that the load capacitance of the respective clock buffers and the wiring resistance until the respective sequential circuits are irregular. For this reason, the conventional semiconductor integrated circuit has a problem that a clock skew between the sequential circuits is large. In particular, if a large macro is placed, the clock wiring bypasses a macro area of the large macro. Hence, the irregular situation becomes more conspicuous. Also, since the transistor dimensions of the respective cells are equal to each other, a gate capacitance of a clock gate portion of the sequential circuit is larger than that of a block for a cell base, which results in a problem of an increase in an electric power consumption.
On the other hand, in the master slice type semiconductor integrated circuit shown in
FIG. 3
, the sequential circuits are collectively arranged in the dedicated area near a clock driver. Therefore, as the number of the sequential circuits is increased, the area for the sequential circuits is increased. Consequently, a distance between the nearest sequential circuit and the farthest sequential circuit is increased, which brings about a severe influence caused by a wiring resistance, which results in a problem that a clock skew between the sequential circuits becomes larger. In particular, as the size of the sequential circuits in the entire circuit becomes larger, the clock skew is increased. Also, if the number of the sequential circuits is known in advance in the custom design, the sequential circuits can be uniformly assigned to the respective clock buffers. However, if the configuration shown in
FIG. 3
is applied to a design of the semi-custom semiconductor integrated circuit such as a gate array, it is difficult to uniformly assign the sequential circuits to the respective clock buffers. If the sequential circuits are excessively assigned in anticipation of a margin, load capacitance (wiring capacitance and gate capacitance) of the clock buffer is increased, which results in a problem of an increase in the electric power consumption. Also, if trying to cope with a poliphase clock, it is difficult to establish the area dedicated to the sequential circuit. Moreover, the uselessness of the electric power consumption becomes large.
As the related art, Japanese Laid Open Patent Application (JP-A-Heisei 6-244282) discloses a technique for attaining an extremely small clock skew, in a semiconductor integrated circuit apparatus having a clock synchronization circuit that is highly integrated and made into a large scale. In this semiconductor integrated circuit apparatus, a clock driver for outputting a clock signal and a plurality of grid-shaped wiring structures are connected such that their wiring lengths are equal, and a low order clock tree structure composed of slave buffers, flip-flops and the like are connected in a grid-shaped wiring structure. Consequently, it is possible to suppress even the clock skew between the grid-shaped wiring structures, simultaneously with the clock skew within the grid-shaped wiring structure. Thus, the clock skew in a large area can be reduced.
Japanese Laid Open Patent Application (JP-A-Heisei 10-308450) discloses a semiconductor integrated circuit that can cancel out a delay time difference (a skew) between flip-flops to which a clock signal of a gated clock circuit to suppress an electric power consumption of a clock line is supplied, and a method of designing the same. This semiconductor integrated circuit is the gated clock circuit having a clock tree structure constituted by a combination of a route buffer, a plurality of stages of buffers sequentially branched from the route buffer and final stage multi-input gates (NOR gates). Its connection relation is established after the arrangements of all cells. Also, after the flip-flops connected to the clock line are clustered for each function, the clustering is further carried out between the nearby flip-flops arranged in the neighborhood. Consequently, the loads, which are driven by the respective buffers and the multi-input gates, become constant. This design can cancel out the skew.
Japanese Laid Open Patent Application (JP-A-Heisei 11-111850) discloses a clock supplying circuit having a configuration that can easily reduce the clock skew, and its layout method and a semiconductor integrated circuit apparatus. The clock supplying circuit includes a first buffe
Maeda Naotaka
Mizuno Masaharu
Sakai Shigeki
Le Don
NEC Electronics Corporation
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