Semiconductor integrated circuit and its design methodology

Details Semiconductor integrated circuit and its design methodology Semiconductor integrated circuit and its design methodology

2005-06-14

2005-06-14

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S738000

Reexamination Certificate

active

06907585

ABSTRACT:
A method and device are provided for applying logic BIST at speed for large-scale and high-performance logic circuits without increasing test time, and decreasing test costs as a result. In one example, a logic BIST controller is divided into two portions. A clock signal having a small delay is used to drive a partial circuit that supplies a user circuit with a scan enable signal and a clock signal. A clock signal having a large delay is used to drive a partial circuit that supplies the user circuit with a test pattern and collects a test result.

REFERENCES:
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patent: 6216254 (2001-04-01), Pesce et al.
patent: 6484294 (2002-11-01), Kiyoshige et al.
patent: 6536024 (2003-03-01), Hathaway
Yervant Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices”, IEEE, Mar. 1993, pp. 4-9.
“Design for AT-Speed Test, Diagnosis and Measurement” (textbook), Chapter 3 Logic Test and Diagnosis, pp. 86-89.

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