Semiconductor integrated circuit and integrated circuit system

Details Semiconductor integrated circuit and integrated circuit system Semiconductor integrated circuit and integrated circuit system

2000-12-19

2002-07-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S230060

Reexamination Certificate

active

06414885

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 USC §119 to Japanese Patent Application No. 1999-375843, filed on Dec. 28, 1999, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit and an integrated circuit system. More particularly, the invention relates to a semiconductor integrated circuit which is preferable to relieve faulty regions in a memory space, and an integrated circuit system including such a semiconductor integrated circuit mounted on a mounting board.
2. Description of the Related Art
A dynamic random access memory (called the “DRAM”) which is a typical example of a readable/writable semiconductor memory tends to have a large capacity in response to increased integration. A memory cell for storing one-bit data of the DRAM is constituted by a series circuit including switching elements and data storing capacitive elements. A plurality of memory cells are arranged in the shape of matrix at intersections of a plurality of data lines and a plurality of word lines, thereby forming a memory space (a memory cell array).
One of technical problems related to such a DRAM is to improve yield in a semiconductor manufacturing process. It is assumed here that one memory cell is faulty. Such a faulty memory cell cannot be accessed at random during writing or reading data, so that the DRAM is judged to be defective. Further, even if one data line or one word line is disconnected, a plurality of memory cells (i.e. a memory cell block) belonging to the disconnected data line or word line cannot be accessed at random during writing or reading data. Therefore, the DRAM is judged to be defective. Usually, the DRAM is provided with a spare redundancy circuit in addition to the memory space in order to relieve faulty regions and improve the manufacturing yield.
On the other hand, a NAND type electrically erasable non-volatile memory (called the “EEPROM”) which is a typical read-only semiconductor memory tends to have a large capacity due to increased integration similarly to the foregoing DRAM. A memory cell for storing one-bit data of the EEPROM comprises a MOSFET (metal oxide semiconductor field effect transistor) having a floating gate electrode as a data storing section. Several or several ten memory cells are connected in series, arranged between data lines and source lines, and connected to word lines. Similarly to the DRAM, the memory cells are arranged in the shape of a matrix in order to constitute a memory space.
In the EEPROM, it is acceptable that there are faulty regions in the memory space. The EEPROM stores data of faulty regions and normal regions in each block unit or each address unit, and control operations are performed so as not to access the faulty regions. The data of the faulty regions and normal regions are stored in a controller outside the EEPROM, thereby preventing the faulty regions of the EEPROM from being accessed.
The foregoing semiconductor memory seems to suffer from the following problems.
Provided with the redundancy circuit in order to relieve the faulty region in addition to the memory space, the DRAM has to increase a semiconductor chip area, and is difficult to promote high integration and capacity increase.
Further, if there are more faulty regions in the memory space of the DRAM than the predetermined quantity allowable in the redundancy circuit, it is not always possible to relieve such faulty regions. As a result, the DRAM will be judged to be defective, which reduces the yield of a semiconductor manufacturing process.
The foregoing problem is not peculiar to the DRAM. For instance, a readable/writable semiconductor memory such as a static type random access memory (called the “SRAM”) also suffers from the similar problem.
On the other hand, addresses in the memory space become non-contiguous, and address control is complicated in the EEPROM since data reading is controlled by escaping addresses of faulty regions.
Further, since the faulty regions are also accessed in the memory space of the EEPROM, access time is unnecessarily increased, and read-out speed is lowered.
Such problems are also noted in an ultra violet erasable non-volatile memory (EPROM) and a read-only memory (ROM).
SUMMARY OF THE INVENTION
The present invention is aimed at overcoming the foregoing problems of the related art. It is an object of the invention to provide a semiconductor integrated circuit and an integrated circuit system which can relieve faulty regions and promote circuit integration.
A further object of the invention is to provide a semiconductor integrated circuit and an integrated circuit system which can accelerate operation.
A still further object of the invention is to provide a semiconductor integrated circuit and an integrated circuit system which can relieve faulty regions during a manufacturing process, accelerated tests, use by users, and so on.
A final object of the invention is to provide a semiconductor integrated circuit and an integrated circuit system which can improve yield of a manufacturing process by relieving faulty regions.
According to a first feature of the invention, a semiconductor integrated circuit comprises a circuit for outputting address data of a part of normal regions in a memory space on the basis of received address data of a faulty region in the memory space, and controlling the relief of the faulty region using the part of normal regions of the memory space as a redundancy region.
In this specification, the term “memory space” denotes a memory cell array where data can be written in and read from memory cells arranged in the shape of matrix, and refers to both two-dimensional and three-dimensional memory spaces. The DRAM, SRAM and so on are readable/writable memory cells. The ROM, EEPROM, EPROM and so on are read-only memory cells. The memory space constituted by these memory cells is used as a memory space of a memory chip, as a memory space included in a logic chip, as a memory space mounted on a memory board or a logic board. The term “normal region” represents a memory cell or a plurality of memory cells (or memory block) where data are normally read and written. The term “faulty region” represents a memory cell or a plurality of memory cells where data cannot be normally read and written. The term “redundancy region” represents a relief region which can relieve a faulty region in the memory space by using a part of the normal regions of the memory space. In this memory cell array controller, the parts of normal regions usable as the redundancy regions are variable with the number of faulty regions.
According to a second feature of the invention, a semiconductor integrated circuit comprises: (a) a faulty address storing table unit for storing address data of a faulty region of a memory space; (b) a replace address storing table unit for storing replace address data in which the address data of the faulty region are replaced with address data of a part of a normal region of the memory space; (c) a first address agreement/disagreement detecting circuit for detecting whether or not the address data of the faulty region stored in the faulty address storing table unit agree with an address signal; and (d) an address data selecting circuit for outputting the replace address data stored in the replace address storing table unit when the address data of the faulty region agree with the address signal, or outputting the address signal when the replace address data do not agree with the address signal. Further, the second feature of the invention, the semiconductor integrated circuit comprising a second address agreement/disagreement detecting circuit for outputting an invalid address signal when said replace address data agree with said address signal.
In accordance with a third feature of the invention, there is provided an integrated circuit system comprising: (a) a first semiconductor memory including at least a first memory space and a first address d

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