Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-02-27
2007-02-27
Kerveros, James C. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C327S158000, C331S017000
Reexamination Certificate
active
10823581
ABSTRACT:
The invention provides a semiconductor integrated circuit for communication control and a wireless communication system using the same realizing reduction in the size of a chip and the size of a module by enabling trimming data to be written into a nonvolatile memory without increasing the number of external terminals. A rewritable nonvolatile memory is provided in a semiconductor integrated circuit, characteristics of circuits including an electronic part are measured and trimming data for correcting variations in the characteristics is stored in the nonvolatile memory. A pin and an interface circuit such as a test pin and a JTAG interface circuit which are originally provided for the semiconductor integrated circuit also serve as an input pin and an interface circuit for sending and storing the trimming data to the nonvolatile memory.
REFERENCES:
patent: 6768955 (2004-07-01), Gauthier et al.
patent: 6975840 (2005-12-01), Lin
patent: 10-041746 (1998-02-01), None
Kitamura Teruo
Kojima Hirotsugu
Kerveros James C.
Miles & Stockbridge PC
Renesas Technology Corp.
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